Processor Architectures & Interfacing - May 2015

Information Technology Engineering (Semester 4)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.

Answer any one question from Q1 and Q2

1 (a) Differentiate between procedure and macro.(6 marks) 1 (b) Explain difference between 80386 pipelined and non-pipelined bus cycle with neat diagram.(6 marks) 2 (a) Explain the following assembler directives:
(i) Public and Extrn
(ii) .Org
(iii) : Model(6 marks) 2 (b) State and explain the significance of any three interrupt related signals of the 80386.(6 marks)

Answer any one question from Q3 and Q4

3 (a) Draw and explain the logical address to physical address translation with paging in 80386 processor.(6 marks) 3 (b) What is virtual mode ? How to switch from protected mode to virtual 86 mode.(6 marks) 4 (a) Write down the steps to switch from Real Mode (RM) to Protected Mode (PM).(6 marks) 4 (b) Explain the difference between 3 operating models of 80386.(6 marks)

Answer any one question from Q5 and Q6

5 (a) Identify and justify addressing mode of the following 8051 Instructions:
(i) MOV @ RO, A
(ii) MOV B, 50H
(iii) DIV AB.(6 marks) 5 (b) List SFR?s used in 8051. Draw and explain SCON and TCON.
(7 marks) 6 (a) Explain the following instructions in 8051:
(i) MUL AB
(ii) SWAP A
(iii) MOV.DPTR, #3000H(6 marks) 6 (b) List the features of 8051 microcontroller. Draw and explain architecture of 8051.(7 marks)

Answer any one question from Q7 and Q8

7 (a) How many interrupts are there in 8051? List them according to their priority. Explain the IP register structure.(7 marks) 7 (b) Explain any two operating modes of timer used in 8051.(7 marks) 8 (a) List and classify 8051 interrupts.(7 marks) 8 (b) Draw and explain formats of SBUF and IE.(6 marks)