Subject: Digital System Design

Topic: Sequential logic design practices

Difficulty: High

A bidirectional, or reversible, shift register is one in which the data can be shift either left or right. A four-bit bidirectional shift register using SR flip-flops is shown below.

The Logic Diagram and Truth Table indicate the functional characteristics of the 74194 4-Bit Bidirectional Shift Register. All data and mode control inputs are edge-triggered, responding only to the LOW to HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse.

The register is fully synchronous, with all operations taking place in less than 15 ns (typical) making the device especially useful for implementing very high speed CPUs, or the memory buffer registers. The four parallel data inputs (P0, P1, P2, P3) are D-type inputs.

When both S0 and S1 are HIGH, the data appearing on P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and Q3 outputs respectively following the next LOW to HIGH transition of the clock. The asynchronous Master Reset (MR), when LOW, overrides all other input conditions and forces the Q outputs LOW.

Two mode control inputs (S0, S1) determine the synchronous operation of the device. As shown in the Mode Selection Table, data can be entered and shifted from left to right (shift right, Q0 º Q1, etc.) or right to left (shift left, Q3 º Q2, etc.), or parallel data can be entered loading all four bits of the register simultaneously. When both S0 and S1,are LOW, the existing data is retained in a “do nothing” mode without restricting the HIGH to LOW clock transition. D-type serial data inputs (DSR, DSL) are provided on both the first and last stages to allow multistage shift right or shift left data transfers without interfering with parallel load operation.