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Explain clock generation techniques in integrated circuits
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written 5.6 years ago by |
Clock generation
The simple inverter based cascade produces complementary clocks Φ and ϕ ̅ from the signal input clock signal.
The figure below shows a simple RS-FF clock generator that generates clk1 and clk2 from original clock signals.
In order to improve the driving ability of clock generator, they are buffered. The figure below shows buffered clock generator. This would increase the time between the rising edges.