Consider CMOS circuit with following parameters $v_{DD}=3.3v,v_{TO}=0.6v,v_{TO},p=-0.7v,K_n=200 \mu A/v^2,K_p=80 \mu A/v^2 $Calculate noise margins of the circuit consider KR=2.5

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written 6.8 years ago by

hetalgosavi • 1.7k

• modified 5.7 years ago

Subject: Basic VLSI Design

Topic: MOSFET Inverters

Difficulty: High

vlsi design

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1 Answer

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written 5.7 years ago by

hetalgosavi • 1.7k

Here Kn ≠ Kp

|VT0, n| ≠ |VT0,p|

Therefore, this is an Asymmetric Inverter.

$k_R$ = 2.5 …..given

Step 1: Find VOH

VOH = VDD = 3.3 V

Since Vin = 0 ….. (nMOS – Cutoff, pMOS - conducting)

Therefore, Vout = VOH = VDD = 3.3 V

Step 2: Find VOL

Since, Vin = VDD = 3.3 V

pMOS is in cutoff and nMOS is conducting

Vout = VOL = 0 V

Step 3: Find VIL

When Vin = VIL

nMOS (saturation) = pMOS (linear)

Step 4: Find VIH

When Vin = VIH

nMOS (Linear) = pMOS (saturation)

Step 5: Noise margins

High noise margin = $NM_H$ = VOH – VIH = 1.75 V

Low noise margin = $NM_L$ = VIL – VOL = 1.08 V

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