Data Transfer Techniques

• Data transfer between CPU and the I/O devices may be done in any of the three possible ways:

1. Programmed I/O.

2. Interrupt- initiated I/O.

3. Direct memory access (DMA).

1. Programmed I/O: • It is due to the result of the I/O instructions that are written in the computer program. Each data item transfer is initiated by an instruction in the program. Usually, the transfer is from a CPU register and memory. In this case, it requires constant monitoring by the CPU of the peripheral devices.

Example of Programmed I/O:

• In this case, the I/O device does not have direct access to the memory unit. A transfer from I/O device to memory requires the execution of several instructions by the CPU, including an input instruction to transfer the data from device to the CPU and store instructions to transfer the data from the CPU to memory.

• In programmed I/O, the CPU stays in the program loop until the I/O unit indicates that it is ready for data transfer. This is a time-consuming process since it needlessly keeps the CPU busy.

The overall operation of the programmed I/O can be summaries as follow:

• The processor is executing a program and encounters an instruction relating to I/O operation.

• The processor then executes that instruction by issuing a command to the appropriate I/O module.

• The I/O module will perform the requested action based on the I/O command issued by the processor (READ/WRITE) and set the appropriate bits in the I/O status register.

• The processor will periodically check the status of the I/O module until it finds that the operation is complete.

The drawback of the Programmed I/O:

• The main drawback of the Program Initiated I/O was that the CPU has to monitor the units all the time when the program is executing. Thus, the CPU stays in a program loop until the I/O unit indicates that it is ready for data transfer. This is a time-consuming process, and the CPU time is wasted a lot in keeping an eye on the executing of the program.

• To remove this problem an Interrupt facility and special commands are used.

2. Interrupt Initiated I/O: (Interrupt Driven I/O)

• Since in Programmed I/O case we saw the CPU is kept busy unnecessarily. This situation can very well be avoided by using an interrupt-driven method for data transfer.

• By using interrupt facility and special commands to inform the interface to issue an interrupt request signal whenever data is available from any device. • In the meantime, the CPU can proceed with any other program execution. The interface meanwhile keeps monitoring the device.

• Whenever it is determined that the device is ready for data transfer it initiates an interrupt request signal to the computer. Upon detection of an external interrupt signal the CPU stops momentarily the task that it was already performing, branches to the service program to process the I/O transfer, and then return to the task it was originally performing.

• A peripheral device sends an interrupt request.

• Processor complete the execution of the current instruction.

• Now the processor issued an acknowledgment request.

• The program then branches to Interrupt Service Subroutine/Routine (ISS/ISR) program.

• The return address is stored in the stack. Stored other register contents as per program needs.

• Data transfer between I/O device and memory takes place under ISS.

• Enabled the interrupt system.

• Loading the return address from the stack into the program counter (PC).

• The program then returns to the main program.

The drawback of Interrupt driven I/O:

Both the methods programmed I/O and Interrupt-driven I/O require the active the intervention of the processor to transfer data between memory and the I/O module and any data transfer must transverse a path through the processor. Thus, both these forms of I/O suffer from two inherent drawbacks.

• The I/O transfer rate is limited by the speed with which the processor can test and service a device.

• The processor is tied up in managing an I/O transfer; a num

Direct Memory Access (DMA)

• The data transfer between a fast storage media such as a magnetic disk and a memory unit is limited by the speed of the CPU.

• Thus, we can allow the peripherals to directly communicate with each other using the memory buses, removing the intervention of the CPU. This type of data transfer technique is known as DMA or direct memory access.

• During DMA the CPU is idle and it has no control over the memory buses. The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit.

• On the simplified block diagram, we have a CPU, RAM, a peripheral unit, and a DMA controller. All except the peripheral unit are connected on the same bus.

• As the CPU and the DMA controller

The processor has two pins HOLD and HLDA which are used for DMA operation.

• First, the DMA controller sends a request by making Bus Request (BR) control line high. When MP receives high signal to HOLD pin, it first completes the execution of current machine cycle, it takes few clocks and sends HLDA signal to the DMA controller.

• After receiving HLDA through Bus Grant (BG) pin of DMA controller, the DMA controller takes control over system bus and transfers data directly between memory and I/O without the involvement of the CPU. During DMA operation, the processor is free to perform next job which does not need system bus.

• At the end of data transfer, the DMA controller terminates the request by sending a low signal to HOLD pin and MP regains control of system bus by making HLDA low. DMA Data Transfer Modes:

A). Block Transfer Mode/ Burst Mode

B). Cycle Stealing Mode/ Single-Byte Transfer Mode

C). Demand Transfer Mode

A). Block Transfer Mode/ Burst Mode:

• In this mode, the DMAC is programmed to transfer ALL THE BYTES in one complete DMA operation.

• After a byte is transferred, the CAR and CWCR have adjusted accordingly.

• The system bus is returned to the processor, ONLY after all the bytes are transferred.

• It is the fastest form of DMA but keeps the processor inactive for a long time.

B). Cycle Stealing Mode/ Single-Byte Transfer Mode:

• Once the DMAC becomes the bus master, it will transfer only ONE BYTE and return the bus to the processor. As soon as the processor performs one bus cycle, DMAC will once again take the bus back from the processor.

• Hence both DMAC and processor are constantly stealing bus cycles from each other.

• It is the most popular method of DMA because it keeps the processor active in the background.

• This mode is used by all modern computers, which allows systems to transfer blocks of data using DMA as well as processors can do other tasks.

C). Demand Transfer Mode:

• It is very similar to Block Transfer, except that the DREQ must remain active throughout the DMA operation.

• If during the operation DREQ goes low, the DMA operation is stopped, and the busses are returned to the processor.

• In the meantime, the processor can continue with its own operations. Once DREQ goes high again, the DMA operation continues from where it had stopped.