Subject: Microprocessors and Applications

Topic: 80806 Interrupts

Difficulty: Medium

Interrupt Vector Table (IVT):

• The interrupt vector table is the link between an Interrupt type code and the procedure that has been designated to service interrupts associated with that code.
• The address pointer table contains 256 address pointers (type ) which are identified as type 0 to type 255 .
• The first 1KB of memory of 8086 (00000H to 003FFH) is set aside as a table for storing the starting addressess of Interrupt Service procedures (ISP ).
• Since 4 bytes are required for storing the address of ISP (2 bytes for IP and 2 bytes for CS ) ,the table can hold 256 Interrup procedures.

• In this table .IP value is put in as low word of the vector and CS is put in high vector.

  IVT is divided into 3 parts

  Dedicated Interrupts (Type 0 to Type 4)

  Reserved Interrupts (Type 5 to Type 31)

  Available Interupts (Type 32 to Type 255)

Dedicated Interrupts :

These Interrupts are dedicated for special purpose which is given below :

Type 0 : Divide by zero Interrupt :

8086 supports division (Unsigned /signed )instructions,8086 will automatically do a type 0 interrupt if the result of DIV or IDIV operation is too large to fit in the destination register. When typr O interrupt is internally generated ,microprocessor will

Push flag register

Reset TF and IF

Push CS and IP (i.e return address )

Get NEW cs and NEW IP . For this microprocessor takes type no i.e ' 0' multiply by  4 .Therefore we get 0×4=0000H0×4=0000H0000H .So the microprocessor gets ,NEW IP 0000H/0001H location and NEW CS from 0002H/0003H location.

NEW CS and NEW IP will be loaded into CS and IP register .Thus we get branching to ISR routine.

After returning from ISR ,microprocessor will pop CS and IP  (OLD CS /OLD IP).Microprocessor will also pop flag register.

Here important point regarding Type 0 ,is it is automatic and cannot be disabled anyway i.e non maskable .User has to keep a account of it in the program where he/she uses DIV/IDIV instruction . Normally user will write an interrupt service procedure which takes desired action when an invalid division occurs. To avoid this interrupt ,user can check ,before division,that divisor is not zero.

Type 1 : Single step Interrupt :

The single step Interrupt is used to debug the program .One can examine the contents of memory/register if required else execute next instruction .

Thus in single stepping mode a system will stop after it executes each instruction and wait for further direction from user.

The 8086 trap flag and type 1 interrupt makes it easy to implement a single step feature.Once TF = 1,microprocessor will automatically do a type 1 interrupt after each instruction executes .

The interrupt sequence saves the flags and program counter ,then resets TF flag to allow the single step routine to execute normally .

To return to the program under test,an interrupt return restores the IP, CS and flags with TF set. When type 1 interrupt is generated in response to the same microprocessor executes same steps which was done for TYPE 0 .

TYPE 2 : NMI (Non Maskable Interrupt )

This is the highest priority hardware interrupt and is non maskable. The input is edge triggered ,but is synchronized with the CPU clock and must be active for two clock cycles to generate recognition.

NMI is non maskable so when this interrupt occurs we have to service this interrupt as we cannot ignore this interrupt .Thus this interrupt is used for very urgent task such as power supply failure.

When type 2 interrupt is generated in response to the same microprocessor executes same steps which was done for TYPE 0 .

TYPE 3 : One Byte Interrupt /Breakpoint Interrupt :

This type is invoked by a special form of the software interrupt instructions which requires a single byte of code space i . e. CCH (INT 3 ).

This interrupt is primarily used as a break point interrupt for software debug .When you insert a break point in your program ,the system executes instructions up to the breakpoint and then goes to the breakpoint procedure.

A breakpoint ISR routine usually saves all the register contents on the stack. At that point system is now waiting for next command from the user.When type 3 interrupt is gnerated in response to the same microprocessor executes same steps which was done for TYPE 0 .

TYPE 4 : Interrupt on Overflow :

This interrupt occurs if the overflow flag (OF) is set in the flag register.It is often placed just after an arithmetic instruction so that special processing will be done if the instruction causes an overflow.

Unlike a divide-by-zero fault, an overflow condition does not cause an interrupt automatically; the interrupt must be explicitly specified by the INTO instruction.

The OF flag is set if the signed result of an arithmetic operation on two signed numbers is too large to be represented in the destination register or memory location . Thus the interrupt is used to capture overflow errors.

One more way of branching to this interrupt is INTO (Interrupt on Overflow ).When type 4 interrupt is generated in response to the same microprocessor executes same steps which was done for TYPE 0 .

Reserved Interrupts : These interrupts are not available to the programmer as they are reserved for future microprocessor.

Available Interrupts : These interrupts are available to the programmer and he can use them as per his requirement .