Design a VHDL Code for Half Subtractor.

0

6.4kviews

Design a VHDL Code for Half Subtractor.

written 7.0 years ago by

snehalshinde • 30

modified 2.9 years ago by

pedsangini276 • 4.8k

Subject: Digital System Design

Topic: Introduction to VHDL

Difficulty: High

digital system design

ADD COMMENT EDIT

1 Answer

0

370views

written 6.7 years ago by

teamques10 ★ 68k

VHDL Code for Half Subtractor:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity hs1 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

diff : out STD_LOGIC;

borrow : out STD_LOGIC);

end hs1;

architecture Behavioral of hs1 is

begin

diff<=a xor b;

borrow<=(not a) and b;

end Behavioral;

ADD COMMENT EDIT

Please log in to add an answer.