Modelling styles in VHDL:

1] Structural modelling: in this type of modelling an entity is explained as a set of inter connected component’s.

• It shows graphical representation of modules component’s, with their inter connection.

• Structural modelling can be used to generate very high level or low level description in ckt.

2] Data flow modelling: In data flow modelling the data flow through the entity is expressed using con current signal assignment statements.

• Concurrent signal assignment statements are those in which appear outside of a process, there are event triggered.

• In signal assignment for assignment of a value to a signal symbol < = is used.

3] Behavioral style of modelling:

• The behavioral level of abstraction is the level of abstraction supported in VHDL.

• Process body must be included in every behavioral description.

• The behavioral style of modelling denotes the entity behavior as a set of statements which executes sequentially.

4] Mixed style of modelling: in a single structure body, we can mix the three modelling style is within an architecture body to represent structure we can use components installation statements, to represent data flow we can use concurrent signal assignment statements and to represent behavior, we can use process statements.