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Design self bias circuit using JFET for midpoint biasing. Let IDSS=8mA,Vp=−3V
1 Answer
written 7.3 years ago by |
Step 1: Circuit Diagram
Step 2: Finding IDSQandVGSQ
Since mid-point biasing is mentioned then,
IDSQ=12IDSS=12×8mA
IDSQ=4mA
We know that,
IDSQ=IDSS(1−VGSQVP)2
4mA=8mA(1+VGSQ3)2
VGSQ=−0.87V
Step 3: Finding Rs
VGS=−IDSQ×Rs
−0.87=−4mA×Rs
Rs=217.5Ω
Step 4: Finding Rd
Apply KVL from VDD to Ground,
VDD−IDSQ(Rd+Rs)−VDSQ=0
Since mid point biasing is mentioned,VDSQ=12VDD
VDD−VDSQ=IDSQ(Rd+Rs)
VDD−12VDD=IDSQ(Rd+Rs)
12VDD=IDSQ(Rd+Rs)
12VDD=4mA(Rd+217.5)
Assume, VDD=20V
10=4mA(Rd+217.5)
Rd=2.28KΩ
Step 5: FindingRG
As JFET Gate and Source is reverse bias it offers very high input impedance in MΩ
Hence,
RG=1MΩ
Step 6: Designed Circuit Diagram