Step 1: Circuit Diagram

Step 2: Finding $I_{DSQ} and V_{GSQ}$

Since mid-point biasing is mentioned then,

$I_{DSQ}=\frac{1}{2}I_{DSS}=\frac{1}{2}\times8mA$

$I_{DSQ}=4mA$

We know that,

$I_{DSQ}=I_{DSS}(1-\frac {V_{GSQ}}{V_P})^2$

$4mA=8mA(1+\frac{V_{GSQ}}{3})^2$

$V_{GSQ}=-0.87V$

Step 3: Finding Rs

$V_{GS}=-I_{DSQ}\times R_s$

$-0.87=-4mA\times R_s$

$R_s=217.5\Omega$

Step 4: Finding Rd

Apply KVL from $V_{DD}$ to Ground,

$V_{DD}-I_{DSQ}(Rd+Rs)-V_{DSQ}=0$

Since mid point biasing is mentioned,$V_{DSQ}=\frac{1}{2}V_{DD}$

$V_{DD}-V_{DSQ}=I_{DSQ}(Rd+Rs)$

$V_{DD}-\frac{1}{2}V_{DD}=I_{DSQ}(Rd+Rs)$

$\frac{1}{2}V_{DD}=I_{DSQ}(Rd+Rs)$

$\frac{1}{2}V_{DD}=4mA(Rd+217.5)$

Assume, $V_{DD}= 20V$

10=4mA(Rd+217.5)

$Rd=2.28K\Omega$

Step 5: Finding$ R_G$

As JFET Gate and Source is reverse bias it offers very high input impedance in $M\Omega$

Hence,

$R_G=1M\Omega$

Step 6: Designed Circuit Diagram