Integrated Circuits - Dec 2015

Electronics & Telecom Engineering (Semester 4)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks.

Solve any one question from Q1 and Q2

1 (a) The following specifications are given for the DIBO differential amplifier:
R_E=4.7 kΩ, R_C=2.2 kΩ, R_in1=R_in2=50Ω, V₈=±10 V and the transistor with β_ac=β_dc=100 with V_BE=0.7 V.
i) Determine the I_CQ and V_CEQ values.
ii) Determine the voltage gain.(6 marks) 1 (b) With neat circuit, explain the dominant pole frequency compensation technique.(6 marks) 2 (a) Design a DIBO differential amplifier with a constant current bias using diodes to satisfy the following requirements:
Differential voltage gain Ad=±10
Current supplied by the constant bias circuit=4 mA
Supply voltage V_S=±12V.(6 marks) 2 (b) Write a note on noise in op-amp.(6 marks)

Solve any one question from Q3 and Q4

3 (a) Explain virtual ground concept and virtual short concept.(6 marks) 3 (b) With neat circuit diagram and waveforms, explain working of half wave precision rectifier.(6 marks) 4 (a) Explain sample and hold circuit using op-amp.(6 marks) 4 (b) What are the limitations of ideal integrator? How are they overcome in practical integrator?(6 marks)

Solve any one question from Q5 and Q6

5 (a) With neat circuit diagram, explain current to voltage converter.(5 marks) 5 (b) Draw the neat circuit diagram of R-2R ladder digital to analog converter (DAC) and explain its working.(5 marks) 5 (c) What output voltage would be produced by a D/A converter whose output range is 0 to 10 V and input binary number is:
i) 10 (for a 2-bit DAC converter)
ii) 0110 (for a 4-bit DAC)
iii) 10111100 (for a 8-bit DAC).(3 marks) 6 (a) Explain the operation of successive approximation type analog to digital converter.(5 marks) 6 (b) With neat circuit diagram, explain V to I converter with grounded load.(5 marks) 6 (c) List various specification of ADC.(3 marks)

Solve any one question from Q7 and Q8

7 (a) (i) Explain:
Digital phase comparator used in PLL.(5 marks) 7 (a) (ii) Explain:
PLL as a FSK demodulator.(5 marks) 7 (b) For LM317 adjustable voltage regulator, R₁=240 Ω and R_{=2 kΩ. If Iadj=50 μA and Vref=1.25 V. Find value of Vo.}(3 marks) 8 (a) Define the following terms with reference to PLL:
i) Free running frequency
ii) Lock range
iii) Capture range
iii) Capture range
iv) Pull-in-time.(10 marks) 8 (b) Explain low drop-out regulator.(3 marks)