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Sequence Detector

• A Sequence detector is a sequential state machine used to detect consecutive bits in a binary string.
• To do this it takes an input string of bits and generates an output of 1 whenever the target sequence has been detected.
• Finite State Machine (FSM), an important category of sequential circuits, is used frequently in designing digital systems.
• There are two main FSM models for sequential circuits:
  • Mealy Model - In this type of circuit the output depends on the external inputs and the current state of the machine.
  • Moore Model - In this type of circuit the output of the system only depends on the current state of the machine.
• There are two types of sequence detectors depending on the type of sequence they identify, which are as follows:

Overlapping Sequence Detector:

• In this type of sequence detector allows overlap, the final bits of one sequence can be the start of another sequence.
• For example, will be an 1101 sequence detector. It raises an output of 1 when the last 4 binary bits received are 1101.

Non-Overlapping Sequence Detector:

• In this type of sequence detector does not allow overlap, but resets itself to the start state when the sequence has been detected.
• For example, after the initial sequence 1101 has been detected, the detector with no overlap resets and starts searching for the initial 1 of the next sequence.

Here, we see Non-Overlapping Mealy Sequence Detector for the sequence 1101 in detail.

State diagram for 1101 sequence detector using Mealy machine (Non - Overlapping):

• Required less number of states as compared with Moore.

State table for 1101 sequence detector using Mealy machine (Non - Overlapping):

• Output in a Mealy sequential circuit is associated with a current state and external inputs X.

Excitation table for 1101 sequence detector using Mealy machine (Non - Overlapping):

• Output depends on the current input and current state of the circuit.

Block diagram for 1101 sequence detector using Mealy machine (Non - Overlapping):

• Mealy circuit is associated with a transition between states.
• Asynchronous output generation though the state changes synchronously to the clock.
• Faster, the output is generated on the same clock cycle.
• Glitches can be generated as output change depends on input transition.
• Unsynchronized input may result in an invalid output is a major drawback of mealy.