Mumbai University > Electronics Engineering > Sem 4 > Discrete Electronic Circuits

Marks: 5M

Year: Dec 2016

Step 1: Circuit Diagram

Step 2: Finding -VGG

We know that,

$IDSQ=IDSS( 1 - \frac{VGSq}{V_p})^2$

$3mA = 10 mA (1+\frac{VGSq}{6})^2$

$VGSq = -2.71V$

For Fixed bias, $VGG = VGSq = -2.71V$

Step 3: Finding $R_D$

Apply KVL from VDD to Ground through drain to source,

$VDD - IDS \times R_D - VDSq = 0$

Assume mid-point biasing, $VDSq = \frac{1}{2}VDD$

$VDD - \frac{1}{2} VDD = IDS \times R_D$

Assume $VDD = 20V$

$10 = 3mA \times R_D$

$R_D = 3.33K\Omega$

Step 4: Finding $R_G$

As JFET Gate and Source is reverse bias it offers very high input impedance in MΩ.

Hence,

$R_G = 1M\Omega$

Step 5: Designed circuit diagram