written 7.7 years ago by | modified 2.8 years ago by |
Mumbai University > Electronics Engineering > Sem 4 > Discrete Electronic Circuits
Marks: 5M
Year: May 2016
written 7.7 years ago by | modified 2.8 years ago by |
Mumbai University > Electronics Engineering > Sem 4 > Discrete Electronic Circuits
Marks: 5M
Year: May 2016
written 7.7 years ago by |
The given circuit diagram is Negative Clamper with negative reference voltage.
Figure 1: Input Waveform
Figure 2: Output Waveform
During positive half cycle, diode will become forward bias and capacitor will starts charging towards $V_m = 5V$ with left plate +ve and right plate -ve. Hence output voltage will be -2V.
During the negative half cycle, the diode becomes reverse-biased and acts as an open-circuit. Thus, there will be no effect on the capacitor voltage. The resistance R, being of very high value, cannot discharge C a lot during the negative portion of the input waveform. Thus during negative input, the output voltage will be the sum of the input voltage and the capacitor voltage and is equal to $-V-(V-V_O)$ or $-(2V-V_O)$ = $-12V$.