VLSI Design - Dec 2013

Electronics Engineering (Semester 7)

TOTAL MARKS: 100
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any four from the remaining questions.
(3) Assume data wherever required.
(4) Figures to the right indicate full marks. 1 (a) Consider a MOS capacitor made on p - type substrate with a doping of 10¹⁶/cm³. The SIO₂ thickness is 500 A^o and the metal gate is made up of aluminium. Calculate the minimum capacitance at threshold.(5 marks) 1 (b) An NMOS with V_T of 1.5 V is operated as V_GS=5V and I_DS=100 ?A. Determine if the MOSFET is in the linear region or saturation region. Assume that K= 20?A/V^2.(5 marks) 1 (c) Consider a resistive load NMOS inverter with an output voltage of 0.2 V when the input is V_OH=V_DD=5V. Find the DC power dissipation of the circuit.(5 marks) 1 (d) "Two critical voltage points on the voltage transfer characteristics of a realistic inverter are identified at points where the slope of V_OUT and V_IN characteristic becomes equal to -1?. Justify the selection of these critical voltage points based on the noise considerations.(5 marks) 1 (e) Explain the layout design rule for minimum gate extension of polysilicon over active and the problems faced in case of violation of rule during fabrication. Draw appropriate diagrams.(5 marks) 2 (a) Explain the various parameters affecting the threshold voltage of a MOS structure. Also explain the influence of substrate bias and ion implantation (in the channel region) on the threshold voltage of the device.(10 marks) 2 (b) Consider an n-channel MOSFET at 300 K with the following parameters:
Channel length = 1.5 ?m, Channel doping = 10¹⁶/ cm³
Channel width = 25 ?m , Oxide thickness = 500 A^o
channel mobility ?_n=600 cm²/Vs, Oxide charge =10^-11 cm ²
Metal SC work function difference ?_ms= -1.13V.
Calculate the saturation current of the device at the gate bias of 5V.(10 marks) 3 (a) Derive an expression for the switching voltage of a CMOS inverter. Design a CMOS inverter with a switching voltage of V_DD/2.(10 marks) 3 (b) Draw the schematic and stick diagram of a 2 ? input CMOS NOR gate and determine the sizes of the transistors such that it has approximately same t_PLH and t_PHLas an inverter with the following sizes.
(W/L)_nmos = 0.5?m/0.25?m and (W/L)_pmos = 1.5?m/0.25?m(10 marks) 4 (a) Design a two input NAND gate in NMOS technology based on a reference NMOS depletion load inverter with inverter ratio K_R=4. Draw the stick diagram and mask layout of the circuit designed following the ? based design rules.(10 marks) 4 (b) Compare the passive and active loads in an NMOS inverter circuit stating their advantages and disadvantages.(10 marks) 5 (a) Explain the basic sequence for building a self aligned p-channel MOSFET with the help of appropriate diagrams.(10 marks) 5 (b) Implement circuit for 2:1 multiplexer using transmission gate logic and write Verilog module for the circuit designed.(10 marks) 6 (a) Compare and explain the effect of full scaling and constant voltage scaling MOSFET dimensions, potentials, doping densities and other key device characteristics.(10 marks) 6 (b) Implement of following boolean function in CMOS logic $$Y=\bar{\left(A+D+E\right),(C+B)}$$
Drow the stick diagram of the circuit and find an equivalent CMOS inverter circuit for simultaneously switching of all inputs, assumng that (W/L)_p=15 for all PMOS transisters and (W/L)_n=10 for all nmos transisters.(10 marks) 7 (a) CMOS latch-up and its prevention(10 marks) 7 (b) MOS CV characteristics(10 marks) 7 (c) Short channel Effects(10 marks)