Mumbai University > Electronics and telecommunication engineering > Sem 3 > Analog electronics 1

Marks: 10M

Years: May 15

Calculation for $R_th$ and $V_G$:

Calculation for $V_G$:

$V_G = \frac{(V_DD X R_2)}{(R_1+ R_2 )}$ = $\frac{(16 X 270 X 10^3)}{(2.1 X 10^6+ 270 X 10^3 )}$ = 1.822 V

$V_G$ = 1.822 V

The reduce circuit as shown in fig 5.6.

Calculation for $I_DQ$, $V_S$ and $V_GS$:

$I_S = I_D + I_G$

Since $I_G≈0$

Hence $I_S ≈ I_D$

Applying KVL to gate-source node we get

$V_G- V_GS- I_D R_S = 0$

$V_GS= V_G- I_D R_S$

Now, $I_D= I_DSS (1-V_GS/V_P )^2$

By Substituting,

$I_D= 8m (1-\frac{(1.822 – 1.5k I_D)}{(-4)})^2$

After Simplification,

$I_D= 16.9475 X 10^(-3) - 8.733 I_D + 1.125 X 10^3 I_D^2$

Hence,

$I_D1 = 6.223 X 10^(-3)$ and $I_D2 = 2.415 X 10^(-3)$

FET is in pinch off region and $I_D$=0 at pinch-off region.

Hence, $I_DQ = I_D2$= 2.415mA

And $V_GSQ$ = -1.8V

$V_S= V_G - V_GS$

= 1.822 – (-1.8)

=3.622

Hence,$V_S$= 3.622

Calculation for $V_DSQ$:

Now, Applying KVL to drain-source channel

$V_DD- V_DS- I_DQ ( R_S+ R_D) = 0$

$16 - 2.415 X 10^(-3) (2.4 X 10^3+ 1.5 X 10^3) = V_DSQ$

$V_DSQ$ = 7.306V