Mumbai University > Electronics ana telecommunication engineering > Sem 3 > Analog electronics 1

Marks: 10M

Years: Dec 14

This is JFET voltage divider bias circuit and $I_DSS$ = 12mA,$V_P$ = -3.5V and λ = 0. Let $R_1+ R_2$= 100k, $I_DSQ$ = 5mA and $V_DSQ$ = 5V are given.

For designing we have to find value of $R_1,R_2$ and $R_D$

Find $V_GSQ, V_S and V_G$:

Source voltage $V_S$ = -5 + $I_DQ$ $R_S$= -5 + 5 X 0.5 = -2.5V

Since, $I_DQ$ = $I_DSS$ $(1-\frac{V_GSQ}{V_P})^2$

$5 = 10 (1+\frac{V_GSQ}{3.5})^2$

By solving, $V_GSQ$ = -1.025 Volts

But $V_GSQ= V_G - V_S$

-1.025 = $V_G$ – (-2.5)

$V_G$ = -3.5 V

Find $R_1$ and $R_2$:

Since $I_G$ = 0, current through $R_1$ and $R_2$ will be same and in series with each other. Let this current is $I_1$.

$I_1 = \frac{(V_DD-V_SS)}{(R_1+ R_2 )} = \frac{(5-(-5))}{100k} = 100 µA$

$R_2 = \frac{(V_G-V_SS)}{I_1} = \frac{(-3.5+5)}{(100 X 10^(-6) )} = 15 kΩ$

Hence $R_1$= 100 kΩ - 15 kΩ = 85 kΩ

Find $R_D$:

Apply KVL to the drain source loop

5 + 5 = $I_DQ R_D + V_DSQ + I_DQ R_S$

10 = $I_DQ (R_D + R_S ) + 55 + 5 = I_DQ R_D + V_DSQ + I_DQ R_S$

5 = 5 ($R_D$ + 0.5)

$R_D$ = 0.5 kΩ