Mumbai University > Electronics and Telecommunication Engineering > Sem 3 > Digital Electronics

Marks: 10M

Year: May 2015

D FF to T FF: Refer answer 2 of chap3

SR FF to JK FF: i. Here the given FF is SR FF and the required FF is JKs FF.

ii. J and K will be given as external inputs to S and R. As shown in the logic diagram below, S and R will be the outputs of the combinational circuit.

iii. The truth tables for the flip flop conversion are given below.

iv. The present state is represented by Qp and Qp+1 is the next state to be obtained when the J and K inputs are applied.

v. For two inputs J and K, there will be eight possible combinations. For each combination of J, K and Qp, the corresponding Qp+1 state are found. Qp+1 simply suggest the future values to be obtained by the JK flip flop after the value of Qp.

vi. The truth table for the conversion logic is as shown in table1.

vii. The table is then completed by writing the values of S and R required getting each Qp+1 from the corresponding Qp. That is, the values of S and R that are required to change the state of the flip flop from Qp to Qp+1 are written.