Mumbai University > Electronics Engineering > Sem 3 > Digital circuits and design

Marks: 10M

Year: May 2016

A fault model is an engineering model of something that could go wrong in the costruction or operation of a piece of equipment. From the model the user or designer can predict the consequences of the particular fault.

Basic fault models in digital circuits include:

1)*The stuck-at-fault mode*l: A signal or gate output is stuck at a 0 or 1 value independent of the Inputs to the circuit.

2)The bridging fault model: Two signals are connected together when they should not be: depending on logic circuitry employed this may result in wired-OR or wired-AND logic functions. Since there are 0 potential bridging faults, they are normally restricted to signals that are physically adjacent to model.

3) The transistor faults: This model is used to describe faults for CMOS logic gates. At transistor level, a transistor maybe stuck-short or stuck-open. In stuck-short, a transistor behaves as if it always conducts (or stuck-on). In stuck-open a transistor behaves as if it never conducts (or stuck-off). Stuck-short will produce short between $\ V_{DD} and V_{SS} $.

4)The open fault model: here a wire is assumed broken, and one or more inputs are disconnected from the output that should drive them. As with the bridging circuits, the resulting behavior depends on the circuit implementation.

5)The delay fault model: when the signal eventually assumes the correct value, but more slowly (or rarely, more quickly) than normal.