Mumbai University > Computer Engineering > Sem 3 > Electronic Circuits and Communication Fundamentals

Marks: 10 Marks

Year: May 2015

1.Analog to digital converter are classified into general groups based on the conversion techniques.

2.One technique involves comparing a given analog signal with the internally generated reference voltages. This group includes successive approximation, flash, delta modulation (DM), and adaptive delta modulation and flash type converters.

3.The technique involves changing an analog signal into tie or frequency and comparing these new parameters against known values. This group includes integrator convertors and voltage-to-frequency convertors.

4.Type of ADC’s using various conversion techniques:

I. Single ramp or single slop

II. Dual slope

III. Successive approximation

IV. Flash

5.Consider single slope ADC

• It consists of a ramp generator and BCD or binary counters.

• The figure shown below shows the single slope ADC.

• At the start, the reset signal is provided to the ramp generator and the counters. Thus counters are resettled to 0’s.
• The analog input voltage $V_{in}$ is applied to the positive terminal of the comparator.
• As this is more positive than the negative input, the comparator output goes high. The output of ramp generator is applied to the negative terminal of the comparator.
• The high output of the comparator enables the AND gate which allows clock to reach to the counters and also the high output starts the ramp.
• The ramp voltage goes positive until it exceeds the input voltage. When it exceeds $V_{in}$, comparator output goes low. This disables AND gate which in turn stops the clock to the counters. The control circuitry provides the latch signal which is used to latch the counter date. The rest signal resets the counters to 0’s and also resets the ramp generator. The latched data is then displayed using decoder and a display device.
• Let us consider the practical example to understand the working. Assume that the clock frequency is 1 MHz. There are four BCD counters and the inputs $V_{in}$ is 2.000 V.
• Now let ramp has a slope of 1 V/ms as shown in the figure below. As the input is 2.000 V, the ramp will take 2 ms to reach to 2 V and to stop the clock to the counters.

• frequency of the clock. The number of pulses reaching to the counter in 2 ms is $\dfrac{2 ms}{\bigg(\dfrac{1}{1} MHz\bigg)} =2000$. The comparator output going high will strobe. The latches and send the count to the displays. Inserting a decimal point at the proper point in the seven segment display gives a reading of 2.000. But we want binary output. In such case instead of BCD counters, binary counters must be used, where output will be straight binary coded.

• The main limitations of this circuits are,

  • Its resolutions is less. Hence for applications which required resolution of 9 part in 20,000 or more, this ADC is not stable.
  • Variations in ramp generator due to time, temperature or input voltage sensitivity also cause a lot of problems.