Mumbai University > Computer Engineering > Sem 3 > Electronic Circuits and Communication Fundamentals

Marks: 10 Marfrks

Year: Dec 2015

Operating principles of PLL

Fig. shows the block diagram of PLL. It consists of

1. Phase detector
2. Low pass filter
3. Error amplifier
4. Voltage Controlled Oscillator (VCO)

The phase detector compares the input frequency $f_s$ with the feedback frequency $f_o$ and generates an output signal which is a function of the difference between the phases of the two input signals. The output signal of the phase detector is a dc voltage. The output of phase detector is applied to low-pass filter to remove high frequency noise from the dc voltage. The output of low pass filter without high frequency noise is often referred to as error voltage or control voltage for VCO. When control voltage is zero, VCO is in free-running mode and its output frequency is called as center frequency fc,. The non-zero control voltage results in a shift in the VCO frequency from its free-running frequency, 1.0 to a frequency f, given by $f = f_o+K_v V_C$, where Kv is the voltage to frequency transfer coefficient of the VCO. The error or control voltage applied as an input to the VCO, forces the VCO to change its output frequency in the direction that reduces the difference between the input frequency and the output frequency of VCO.

This action, commonly known as capturing, continues till the output frequency of VCO is same as the input signal frequency. Once the two frequencies are same, the circuit is said to be locked. In locked condition, phase detector generates a constant dc level which is required to shift the output frequency of VCO from center frequency to the input frequency. Once locked, PLL tracks the frequency changes of the input signal. Thus, a PLL goes through three states: free running, capture and phase lock.

Frequency Translation

The frequency translation means shifting the frequency of an oscillator by a small factor. Figure shows the block schematic for frequency translator using PLL.

Block schematic for frequency translator using PLL

It consists of mixer, low pass filter and the PLL. The input frequency fs which has to be shifted is applied to the mixer. Another input to the mixer is the output voltage of VCO, fo. Therefore, the output of mixer contains the sum and difference signal (fo ±f.). The low pass filter connected at the output of mixer rejects the (fo + fs) signal and gives only (fo - fs) signal at the output. The (fo - fs) signal is applied to the phase detector. Another input for phase detector is the offset frequency f1. In the locked mode, the VCO output frequency is adjusted to make two input frequencies of phase detector equal. This gives,

fo - fs =f1

and fo = fs + f1

By adjusting offset frequency f1 we can shift the frequency of the oscillator to the desired value.