JFET is operated in the constant current portion of its output characteristics for the linear applications .
In the region before pinch off , where $V_{DS}$ is small the drain to source resistance rd can be controlled by the bias voltage $V_{GS}$.The FET is useful as a voltage variable resistor (VVR) or Voltage Dependent resistor.
In JFET the drain source conductance $g_d = \dfrac{I_d}{V_{DS}}$ for small values of $V_{DS}$ which may be expressed as $g_d = g_d0 [ 1-( V_{GS} V_p)^{1/2} ]$ where $g_{d0}$ is the value of drain conductance when the bias voltage $V_{GS}$ is zero.
The variation of the $r_d$ with $V_{GS}$ can be closely approximated by $r_d = r_o / 1- KVgs r_o –$ drain resistance at zero gate bias and K constant dependent upon FET type.
Small signal FET drain resistance $r_d$ varies with applied gate voltage $V_{GS}$ and FET act like a Voltage Variable Resistor.
Hence, JFET can be used as a Voltage Variable Resistor.