Mumbai University > Computer Engineering > Sem 3 > Electronic Circuits and Communication Fundamentals

Marks: 10 Marks

Year: May 2014

The figure below shows the n-channel JFET, showing bias voltages, depletion region and current directions:

1) When neither any bias is applied to the gate (i.e. when $V_{GS} = 0$) nor any voltage to the drain w.r.t. source (i.e. when $V_{DS} = 0$), the depletion regions around the P-N junctions, are of equal thickness and symmetrical.

2) When positive voltage is applied to the drain terminal D w.r.t. source terminal S without connecting gate terminal G to supply, as illustrated in fig. the electrons (which are the majority carriers) flow from terminal S to terminal D whereas conventional drain current $I_D$ flows through the channel from D to S.

3) Due to flow of this current, there is uniform voltage drop across the channel resistance as we move from terminal D to terminal S. This voltage drop reverse biases the diode. The gate is more “negative” with respect to those points in the channel which are nearer to D than to S. Hence, depletion layers penetrate more deeply into the channel at points lying closer to D than to S. Thus wedge-shaped depletion regions are formed, as shown in figure. When $V_{DS}$ is applied. The size of the depletion layer formed determines–the width of the channel and hence the magnitude of current $I_D$ flowing through the channel.

4) To see how the width of the channel varies with the variation in gate voltage, let us assume that the gate is negative biased with respect to the source while the drain is applied with positive bias with respect to the source.

5) This is shown in the figure above. The P-N junctions are then reverse biased and depletion regions are formed. P regions are heavily doped compared to the N-channel, so the depletion regions penetrate deeply into the channel. Since a depletion region is a regions depleted of the charge carriers, it behaves as an insulator.

6) The result is that the channel is narrowed, the resistance is increased and drain current $I_D$ is reduced. If the negative voltage at the gate is again increased, depletion layers meet at the center and the drain current s cut-off completely. If the negative bias to the gate is reduced, the width of the depletion layers gets reduced causing decrease in resistance and, therefore, increase in drain current $I_D$ is called the pinch-off voltage $V_p$.

7) It is also to be noted that the amount of reverse bias is not the same throughout the length of the P-N junction. When the drain current flows through the channel, there is a voltage drop along its length.

8) The result is that the reverse bias at the drain end is more than that at the source end making the width of depletion layer more at the drain. To see how the width of the channel varies with the variation in gate, go through the figure above.

9) As increasing levels of negative gate-source voltage will reduce the current flow from source to drain as shown in figure above. Decreasing the amount of negative voltage applied to the gate will cause the current flow source to drain to increase.

10) In the above figure the voltage $V_{GS}$ applied to the Gate controls the current flowing between the Drain and the Source terminals. $V_{GS}$ refers to the voltage applied between the Gate and the Source while $V_{DS}$ refers to the voltage applied between the Drain and the Source.

11) Because a Junction Field Effect Transistor is a voltage controlled device, “NO current flows into the gate!” then the Source current ( $I_S$ ) flowing out of the device equals the Drain current flowing into it and therefore ($I_D = I_S$ ).

12) The characteristics curves example shown above, shows the four different regions of operation for a JFET and these are given as:

• Ohmic Region – When $V_{GS} = 0$ the depletion layer of the channel is very small and the JFET acts like a voltage controlled resistor.
• Cut-off Region – This is also known as the pinch-off region were the Gate voltage, $V_{GS}$ is sufficient to cause the JFET to act as an open circuit as the channel resistance is at maximum.
• Saturation or Active Region – The JFET becomes a good conductor and is controlled by the Gate-Source voltage, ( $V_{GS}$ ) while the Drain-Source voltage, ( $V_{DS}$ ) has little or no effect.
• Breakdown Region – The voltage between the Drain and the Source, ( $V_{DS}$ ) is high enough to causes the JFET’s resistive channel to break down and pass uncontrolled maximum current.