The Pentium has superscalar organizations. It enables 2-instructions to be executed in parallel. Figure below (a) shows that the resources for address generation and ALU functions have been replicated in independent integer pipeline, called U- and V-.

The ????P in the PF and D1 stages can fetch and decode 2-simple instructions in parallel and issue them to the U- and V-pipelines. Additionally, the ????P for complex instructions in D1 can generate micro coded sequences that control both U- and V-pipelines. Several techniques are used to resolve dependencies between instructions that might be executed in parallel. Most of the logic is contained in the instruction issue algorithm as indicated in Figure (b) of D1.

Resource Dependency

When 2-instructions require a single functional unit or data path, a resource dependency occurs. The ????P during the D1 stage issues 2-instructions for parallel execution if both belong to the class of simple instructions, thereby eliminating most resource dependencies. The instructions must be directly executed that does not require micro-coded sequencing. The instruction being issued to the V-pipe can be an ALU operation, memory referencing or a jump. The instruction being issued to the U-pipe can be from the same categories or from an additional set that uses a functional unit available only in the U-pipe, such as the barrel shifter. Although, the set of instructions identified as 'simple' might seem restrictive, more than 90% of the instructions executed in the integer SPEC benchmark suite are simple.

Data dependencies

When one instruction writes a result that is read or written by another instruction, a data dependency occurs. Logic in D1 ensures that the source and the destination registers of the instruction issued to the V-pipe differ from the destination register of instruction issued to the U-pipe. This arrangement eliminates read-after-write (RAW) and write-after-write (WAW) dependencies. Write-after-read (WAR) dependencies need not be checked because reads occur in an earlier stage of the pipelines than writes. The design includes logic that enables instruction with certain special types of data dependency to be executed in parallel. For example, a conditional branch instruction that tests the flag results can be executed in parallel with a compare instruction that sets the flags.

Control dependencies

When the result of one instruction determines whether another instruction will be executed, a control dependency occurs. The ????P in D1 never issues an instruction to the V-pipe when a jump instruction is issued to the U-pipe, thereby eliminating control dependencies.