Mumbai University > Computer Engineering > Sem 5 > Microprocessor

Marks: 10M

Year: May 2015

1. Figure below shows that how an 8259 can be interfaced with the 8086 microprocessor system in minimum mode. In case of 8088 microprocessor same interfacing diagram can be used except M/I0 signal.
2. In 8088, M/IO signal is represented by 10/M signal, therefore this signal is connected to G (active high) signal of decoder to interface 8259A in I/O mapped I/O mode.

1. The 74LS138 address decoder will assert the CS input of the 8259 when an I/O base address is FFF0H or FFF2H on the address bus.
2. The A_0 input of the 8259A is used to select one of the two internal addresses in the device. Ao of the 8259A is connected to system line Al. So the system addresses for the two internal addresses are FFF0H and FFF2H.
3. The data lines of an 8259 are connected to the lower half of the system data bus; because the 8086 expects to receive interrupt types on these lower eight data lines.
4. RD and WR signals are connected to the system RD and WR lines.
5. The interrupt request signal INT from the 8259 is connected to the INTR input of the 8086 and INTA from the 8086 is connected to INTA on the 8259A. As we are using single 8259 in the system SP/EN pin is tied high and CAS0-CAS2 lines are left open.
6. The eight IR inputs are available for interrupt signals.
7. Cascading :
8. The 8259 can be easily interconnected to get multiple interrupts. Fig below shows how 8259 can be connected in the cascade mode. In cascade mode one 8259 is configured in Master mode and other should be configured in the Slave mode. In this figure 8259 is in the master mode and others are in slave mode. Each slave 8259 is identified by the number which is assigned as a part of its initialization. Since the 8086 has only one INTR input, only one of the 8259 INT pins is connected to the 8086 INTR pin. The 8259 connected directly into the 8086 INTR pm is referred as the master. The INT pins from other 8259 are connected to the IR inputs of the master 8259. These cascaded 8259s are referred as slave. The INTA signal is connected to both master and slave 8259.
9. The cascade pins CAS0 to CAS2 are connected from the master to the corresponding pins of the slave. For the master these pins function as outputs, and for the slave these pins function as inputs. The SP/EN signal is tied high for the master. However it is grounded for the slave.
10. Each 8259A has its own addresses so that command words can be written to it and status bytes read from it.

1. Address for 8259s

1. Master and slave operation : When the slave receives an interrupt signal on one of its IR inputs, it checks mask condition and priority of the interrupt request. If the interrupt is unmasked and its priority is higher than any other interrupt level being serviced in the slave, then the slave will send an NT signal to the IR input of a master. If that IR input of the master is unmasked and if that input is a higher priority than any other IR inputs currently being serviced, then the master will send an INT signal to the 8086 INTR input. If the INTR interrupt is enabled, the 8086 will go through its INTR interrupt procedure and sends out two INTA pulses to both the master and the slave. The slave ignores the first interrupt acknowledge pulse but the master outputs a 3-bit slave identification number on the CAS0-CAS2 lines. Sending the 3-bit ID number enables the slave. When the slave receives the second INTA pulse from the 8086, the slave will send the desired type number to the 8086 on the eight data lines. If an interrupt signal is applied directly to one of the IR inputs of the master, the master will send the desired interrupt type to the 8086 when it receives the second INTA pulse from the 8086.