Mumbai University > Computer Engineering > Sem 5 > Microprocessor

Marks: 10M

Year: Dec 2014, Dec 2015

1. The 8237 works in two modes i.e., master and slave modes.
2. In slave mode, the 8237 functions as an input/output device. In this mode the system buses arc controlled by microprocessor and hence the microprocessor is connected to the system bus.
3. In master mode 8237 becomes the bus master and hence the microprocessor is isolated from the system bus. This isolation is done by AEN signal.
4. In minimum configuration, 8237 DMA controller is used to transfer the data. The peripheral chips are interface as normal 10 ports. Figure shows the interfacing of DMA controller with 8086.
5. In minimum mode the HOLD and HLDA signals are used to bus arbitration and in maximum mode configuration RQ_0/GT_0; and RQ_1/GT_1.
6. The 8237 outputs only 16-bit memory address but not the complete 20-bit address of 8086. To store the remaining four address hits A_16—A_19 a separate page latch is required.
7. The 8237 is not compatible with 8086 in its maximum mode configuration. This is because RQ/GT is not compatible with HRQ and HLDA of 8237.
8. So if 8086 is to be interfaced with DMA controller, then 8089 10 processor is required.
9. The 8089 interfaces to the 8086's local multiplexed buses. It shares the bus buffers and system controller of the host system. It is compatible with the RQ/GT signals of 8086 and outputs the complete 20-bit address.

Different data transfer modes of 8237 DMA controller:

The 8237 is in the idle cycle if there is no pending request or the 8237 is waiting for a request from one of the DMA channels. Once a channel requests a DMA service, the 8237 sends the HOLD request to the CPU using its HRQ pin. If the CPU acknowledges the hold request on HLDA, the 8237 enters an active cycle. In the active cycle, the actual data transfer takes place in one of the following transfer modes as is programmed.

1. Single Transfer Mode: In this mode, the device transfers only one byte per request. The word count is decremented and the address is decremented or incremented (depending on programming) after each such transfer. The Terminal Count (TC) state is reached when the count becomes zero. For each transfer the DREQ must be active until the DACK is activated, in order to get recognized. After TC the bus will be relinquished for the CPU. For a new DREQ to 8237 it will again activate the HRQ signal to the CPU and the HLDA signal from the CPU will push the 8237 again into the single transfer mode. This mode is also called as 'cycle stealing'.
2. Block Transfer Mode: In this mode, the 8237 is activated by DREQ to continue the transfer until a TC is reached, i.e. a block of data is transferred. The transfer cycle may be terminated due to EOP (either internal or external) which forces Terminal Count (TC). The DREO needs to be activated only till the DACK signal is activated by the DMA controller. Auto-initialization may be programmed in this mode.
3. Demand Transfer Mode: In this mode, the device continues transfers until a TC is reached or an external EOP is detected or the DREQ signal goes inactive. Thus a transfer may exhaust the capacity of data transfer of an I/O device. After the I/O device is able to catch up the service may be re-established activating the DREQ signal again. Only the EOP generated by TC or external EOP can cause the auto-initialization, and only if it is programmed for.
4. Cascade Mode: In this mode, more than one 8237 can be connected together to provide more than four DMA channels. The HRQ and HLDA signals from additional 8237s are connected with DREQ and DACK pins of a channel of the host 8237 respectively. The priorities of the DMA requests may be preserved at each level. The first device is only used for prioritizing the additional devices (slave 8237s), and it does not generate any address or control signal of its own. The host 8237 responds to DREQ generated by slaves and generates the DACK and the HRQ signals to coordinate all the slaves. All other outputs of the host 8237 are disabled.
5. Memory to memory Transfer: To perform the transfer of a block of data from one set of memory address to another one, this transfer mode is used. Programming the corresponding mode bit in the command word, sets the channel 0 and I to operate as source and destination channels, respectively. The transfer is initialized by setting the DREQ0 using software commands. The 8237 sends HRQ (Hold Request) signal to the CPU as usual and when the HLDA signal is activated by the CPU. the device starts operating in block transfer mode to read the data from memory. The channel 0 current address register acts as a source pointer. The byte read from the memory is stored in an internal temporary register of 8237. The channel 1 current address register acts as a destination pointer to write the data from the temporary register to the destination memory location. The pointers are automatically incremented or decremented, depending upon the programming. The channel 1 word count register is used as a counter and is decremented after each transfer. When it reaches zero, a TC is generated, causing EOP to terminate the service. The 8237 also responds to external EOP signals to terminate the service. This feature may be used to scan a block of data for a byte. When a match is found the process may be terminated using the external EOP. Under all these transfer modes, the 8237 carries out three basic transfers namely, write transfer, read transfer and verify transfer. In write transfer, the 8237 reads from an I/O device and writes to memory under the control of IOR and MEMW signals. In read transfer, the 8237 reads from memory and writes to an I/O device by activating the MEMR and IOW signals. In verify transfers, the 8237 works in the same way as the read or write transfer but does not generate any control signal.