Computer Organization and Architecture - May 2012

Computer Engineering (Semester 4)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks. 1 (a) Consider a cache (M1) and memory (M2) hierarchy with the following characteristics:
M1: 16k words, 50ns access time
M2: 1m words, 400ns access time
Assume 8 words cache blocks and set size of 256 words with the set associative mapping
(i) Show the mapping between M1 and M2
(ii) Calculate the effective access time with a cache hit ratio of h=0.95(10 marks) 1 (b) What do you mean by fetch cycle, instruction cycle, machine cycle and interrupt acknowledgement cycle? Explain in brief. (10 marks) 2 (a) Multiply (-7) and (3) by using Booth's multiplication. Give the flow table of multiplication.(10 marks) 2 (b) What is micro operation? Give some examples of four types of micro-operations.(10 marks) 3 (a) What do you mean by initialization of DMA controller? How DMA controller works? Explain with suitable block diagram.(10 marks) 3 (b) What is virtual memory? Explain how the virtual address is mapped into the physical address?(10 marks) 4 (a) Explain with example, how effective address is calculated in different types of addressing modes.(10 marks) 4 (b) Formulate a four segment instruction pipeline for a computer. Specify the operation to be performed in each segment.(10 marks) 5 (a) Explain any two methods of hard wired control unit.(10 marks) 5 (b) Explain the Von Neumann architecture with the help of diagram.(10 marks) 6 (a) With the neat flow chart, explain the procedure for the division of the floating point numbers carried out in a computer. (10 marks) 6 (b) Explain the Flynn's classification of the parallel processing.(10 marks)

Write short notes on (any four)

7 (a) PCI bus architecture(5 marks) 7 (b) Systolic arrays(5 marks) 7 (c) Compare RISC and CISC(5 marks) 7 (d) IEEE 754 format(5 marks) 7 (e) Programmed I/O(5 marks)