Explain Memory Management in details in 80386DX processor

370views

written 8.0 years ago by

meghalikalyankar • 2.3k

The 80386DX has 32-bit address bus so it can access up to 4 Gbytes (2^32) of memory locations. Figure (a) below shows the physical address space. From the software point of view this memory is organized over the address range from 00000000H through FFFFFFFFH and 80386DX can access data in this memory as byte, word or double words. The words are accessed from two consecutive memory locations whereas double words are accessed from four consecutive memory locations. To implement this entire memory is divided into four independent byte-wide memory banks: Bank0-Bank3. Each bank is 1 Gbyte in size.

enter image description here

Figure (b) shows the organization of four memory banks. As shown in figure bank 0, bank 1, bank 2 and bank 3 are selected using byte enable signals BE0, BE1, BE2 and BE3 signals, respectively.
Address lines A31-A2 are connected in parallel to all memory banks which make it possible to access 1G-byte of memory. But the 32-bit data bus is distributed over four memory banks, 8-bit each.
The 80386 uses byte enable signals instead of the two least significant address bits, because 80386 has problems involved in addressing more than one byte of memory at a time. When 80386 accesses word from even address, it uses two consecutive memory locations for example,

enter image description here

MOV WORD PTR DS: [2000H], 5678H This instruction writes 78 to address 2000H and 56 to address 2001H.
Similarly, when 80386 accesses Dword from address divisible by 4, it uses four consecutive memory locations. This works fine when 80386 accesses even byte in case of word access and address divisible by 4 in case of Dword access, since address on the A31-A2 lines is same for word as well as Dword access.
The data transfers using such addresses are called Aligned transfers. But to access word from odd address or to access Dwords from address not divisible by 4 unaligned 80386 faces problem in placing the correct address on the address bus. This problem is solved by replacing two address pins AO and Al with four byte enable pins.
Without the two least significant address pins, the 80386 produces only addresses that are even multiples of 4. To distinguish between (our addresses (four banks) byte enable signals are used. Table 1.3 shows the use of the four byte enables pins with the address pins.

ADD COMMENT EDIT