Analog & Digital Circuits - Dec 2011

Information Technology (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks. 1(a) Perform 492₍₁₀₎ - 275₍₁₀₎ in BCD using 10's complement(5 marks) 1(b)(i) Simplify: (B+BC)(B+BC)(B+D) (2 marks) 1(b)(ii) Simplify ? m (0, 1,2,3,5,7, 8, 9, 10, 12, 13) using K-map(2 marks) 1(c) Implement the following using decoder
f₁ (A,B,C) = ? m(0,4,7) + d(2,3)
f₂ (A,B,C) = ? m(1,5,6)
f₃ (A,B,C) = ? m(0,2,4,6)(3 marks) 1(d)(i) Write the truth table and excitation table of JK flip flop.(4 marks) 1(d)(ii) Briefly explain CAD tools for Digital Design.(4 marks) 2(a) Minimize ? m(0,1,2,8,9,15,17,21,24,25,27,31) using Quine-McCluskey method. Also find most essential prime implicants.(10 marks) 2(b) Prove that NAND and NOR are universal gates.(10 marks) 3(a) Design a BCD adder.(10 marks) 3(b) Implement Full adder using 8:1 MUX(10 marks) 4(a) Design MOD 12 synchronous counter using JK flip flop.(10 marks) 4(b) Convert: -
SR to D F/F
JK to T F/F(10 marks) 5(a) Given the logic expression AB + AC + C + AD + ABC + ABC
(i) Express in standard SOP form
(ii) Minimize using K-map and realise using only NAND gates.(12 marks) 5(b) Implement following using only one 8:1 MUX and few gates.
F=?m(0,1,3,4,5,7,9,10,12,13,15)(8 marks) 6(a) Design 4-bit asynchronous up/down counter.(10 marks) 6(b) Explain 4-bit bidirectional shift register. What are the uses of register?(10 marks)

Write short notes on any two of the following:-

7(a) ALU(10 marks) 7(b) Priority Encoder(10 marks) 7(c) PAL and PLA(10 marks) 7(d) VHDL features(10 marks)