Digital Logic Design & Analysis - Dec 2011

Computer Engineering (Semester 3)

TOTAL MARKS: 80
TOTAL TIME: 3 HOURS (1) Question 1 is compulsory.
(2) Attempt any three from the remaining questions.
(3) Assume data if required.
(4) Figures to the right indicate full marks. 1(a) Convert (650.17)₈ into decimal, binary and hexadecimal.(6 marks) 1(b) Explain ALU with the help of a block diagram.(6 marks) 1(c) State and explain distributive and associative laws for Boolean expression.(4 marks) 1(d) Determine the truth table for the circuit given in Fig. 1:

(4 marks) 2(a) Design 16:1 MUX using 4:1 MUX.(10 marks) 2(b) Simplify using K-map, obtain minimal SOP equation and realise only by using NAND gates.f(A, B, C, D) = ?M (1,2,3,8,9,10,11,14) + d(7,15) (10 marks) 3(a) Using Quine McCluskey method, determine the minimal SOP form for:F(A,B,C,D,E,F,G) = ? m(20,28,38,39,52,60,102,103,107) (10 marks) 3(b) Design a BCD adder using 4-bit binary adder and explain.(10 marks) 4(a) What is a shift register? Explain 4-bit bidirectional shift register.(10 marks) 4(b) Design a MOD-6 synchronous up counter and explain its operation.(10 marks) 5(a) Implement the following expression using 8:1 MUX:F(A,B,C,D) = π m(0,1,3,6,9,11,12,13,15) (10 marks) 5(b) Explain with a neat diagram 2 input TTL NAND gate in detail.(10 marks) 6(a) Convert T flip-flop to D flip-flop.(10 marks) 6(b) Compare the different logic families with respect to the following parameters - Fan in, Fan out, Noise margin, speed and power dissipation.(10 marks) 7(a) Decade counters:(7 marks) 7(b) DeMorgan's laws:(7 marks) 7(c ) Race around condition:(6 marks)