1) The intel corporation uses the generic name Intel architecture for processor in its product line.

2) IA-32 processor has 32-bit memory addresses and 32-bit data operands. Two successive instructions are dispatched in parallel to the two integer units U and V, which are capable of executing instructions in parallel.

Internal structure of IA-32:

• Fig. above shows simplified Pentium Architecture. It include two on-chip caches, one for data and one for instructions, each of 8k bytes.

• The data cache feeds both integer and floating point operations. The data Cache is dual ported. The code cache is read only, feeds into prefetch buffer.

• The main execution units two integer arithmetic logic units (ALUs) which can ex3ecute in parallel. A floating point units with its own registers and its own multiplier add and divide components.

• The two 32-bit port can be used separately to interface to two integer ALU units and can be combined for a 64-bit interface to floating point unit.

1) It consist of fetch/decode unit, dispatch/execute unit, a high level pipeline. They communicate through an instruction pool. Information in the instruction pool is stored in a table called the Re-order Buffer pool (ROB).

2) The fetch/decode unot fetches instructions and break them into micro-operation for storage in ROB.

3) The dispatch/Execute unit takes micro operations from the ROB and execute them.

4) The retire units complete execution of each micro-operation and updates the registers. Instruction enter the ROB in order, can be executed out of order, but are retired in order again.

5) The bus interface unit is responsible for communicating with the memory system, both the L2 cache and the main memory. The L2 cache is not connected to local bus, so the bus interface unit is responsible for fetching data loading all the caches.