Mumbai University > Electronics Engineering > Sem6 > Computer Organization

Marks: 5M

Year: Dec 2015

1) In single data path the resulting control sequences are quite long because only one data item can be transferred over the bus in a clock cycle.

2) To reduce the number of steps, most of processors provide multiple interval data paths that enables several transfer take place in parallel.

3) The three bus structure is shown in figure. Used to connect the the register & ALU. In VLSI technology, the most efficient way to implement a number of register is in the form of array of memory cell.

4) Buses A and B are used to transfer the source operands to the A and B input of ALU where an arithmetic or logic operation may performed. The result is transferred to the destination over bus c.

5) By providing more paths for data transfer a significant reduction in the number of clock cycles needed to execute an instruction is achived.