Mumbai University > Electronics Engineering > Sem6 > Computer Organization

Marks: 10M

Year: June 2015, Dec 2015

1) To improve the performance of a system is to use faster circuit technology to build the processor and main memory. Another possibility is to arrange the hardware so that more than one operation can be performed at a same time.

2) Pipelining is a particularly effective way of organizing concurrent activity in a computer system.

Consider following figure to understand idea of pipelining:

The fetch unit fetches the instruction I1 and stores it in buffer B1, this is performed in first clock cycle. In the second clock cycle, fetch unit fetches next instruction I2, meanwhile Execute unit executes the instruction I1 .

3) To understand the pipeline performance, let’s consider four stage of pipeline (fetch, Decode, Execute, write operation).

4) Any condition that causes the pipeline to stall is called a hazard. The different types of hazards are as follows:

  a) Data hazards 

  b) Instruction hazards 

 c) Structural hazards

a) Data hazards:

1) Data hazards occurs because one of the pipeline stages may not able to complete its processing task for a given instruction in the time allotted.

2) From above diagram we can figure out that stage E is responsible for arithmetic And logic operation and one clock cycle assigned for this task. But it is not sufficient for some operation. Instruction I2 requires three cycles to execute. Hence write stage w2 must be to do nothing, because it has no data to work.

3) Hence pipeline gets stalled. This is called, data hazards. To avoid to data following techniques are used:

 i) Operand forwarding.

 ii) Avoid data dependency by introducing stages in decode unit.

b) Instruction Hazards:

1) Pipelined may also get stalled because of a delay in the availability f instruction. This may be a result of a miss in the cache, requiring the instruction to be fetched from the main memory. Such hazards is called as instruction hazards.

2) The effect of cache miss on pipelined operation is shown in figure below.

Instruction I1 is fetched from the cache in cycle 1, and its execution proceeds normally. However, the fetch operation for instruction I2 , which is started in cycle 2, results in cache miss. The instruction fetch unit must now suspend any further fetch requests and wait for I2 to arrive. We assume that instruction I2 is received and loaded in to buffer B1 at the end of cycle 5. The pipeline resumes its normal operation at that point.

To avoid instruction hazards following solutions are used

 i) Instruction Queue and prefetching.

 ii) Branch prediction.

C) Structural Hazard:

1) A third type of hazard that may be encountered in pipelined operation is known as a structural hazard. This is the situation when two instructions require the use of a given hardware resource at the same time.

2) The most common case in which this hazard may arise is in access to memory. One instruction may need to access memory as a part of the Execute or write stage while other instruction is being fetched.

3) If instruction and data reside in the same cache unit, only one instruction can proceed and the other instruction is delayed. Many processors use separate instruction and data caches to avoid this delay.

4) Figure below shows how load instruction is accommodated in 4-stage pipeline.

The memory address, X+[R1], is computed in step E2 in cycle 4, then memory access takes place in cycle 5. The operand read from memory is written into register R2 in cycle 6. This means that the execution of this take into two clock cycles (cycle 4 and 5). It causes the pipeline to stall for one clock cycle, because both instruction I2 and I3 require access to the register file in cycle 6. Even through the instructions and their data are all available, the pipelined is stalled because one hardware resources, the register file, cannot handle two operation once.

5) Structural hazards are avoided by providing sufficient hardware resources on the processor chip.