Mumbai University > Electronics Engineering > Sem6 > Computer Organization

Marks: 5M

Year: June 2015

1) In case of cache miss, required data block should be brought form main memory to cache. Before a data block that is present in cache which should be replaced by block of main memory, it is necessary to consider whether it has been modified in cache but not in main memory.

2) If it has not then old block in cache is overwritten by incoming block. If it has been modified, then corresponding block in main memory must be updated accordingly.

3) Hence, care should be taken that contents of cache b;ock and corresponding block in the main memory do not mismatch. Cache coherency should be maintained.

4) There are different techniques to achieve Cache coherency.

• Write Through Technique:-In this Cache location and main memory are updated simultaneously.

• Write Back Technique:- It is used to update only the Cache location to mark it as updated with an associated flag bit, called as Dirty or modified bit. The main memory location of the word is updated later, when the block containing this marked word is to be removed from cache to make a room for a new block.

• Load- Through Technique:-

  • During a read operation, when the addressed word is not in a cache, a read miss occurs. The block of words that contains the requested word is copied from the main memory into particular cache determined by the cache controller. After the entire block is loaded into the cache, the particular word requested is forwarded to CPU. Alternatively this word may be sent to the CPU as soon as it is read from from the main memory.

  • During write operation, If addressed word is not in the cache, a write miss occurs. Then if the write through technique is used, the information is written directly into the main memory. In case of write back technique, the block containing the addressed word is first brought into the cache, and then the desired word in the cache is over written with the new data.

• Cache Flush:- When DMA transfer is made from the main memory to the disk, and the cache uses the write back technique. In thus case, the data in the memory may not show the modifications that may have been made in the cache by forcing the dirty data to be written back to memory before the DMA transfer takes place.

• Snooping:- In snooping, the cache controller invalidates the cache entry if some other master in the system updates a location in shared memory which is also present in the cache.