1. In I/O data transfer, data is transferred by using microprocessor. The microprocessor will read data from I/O device and then will write data to memory.
2. In this case, there are two operations for single data transfer. If the data is less then microprocessor will not waste its time transferring data from I/O to memory or back.
3. But suppose data is huge then the transfer rate from I/O to memory or back will slow down because of microprocessor intervention.
4. In such case, to speed up the process of transferring the data, I/O should have direct access to memory.
5. It can have Direct Memory Access (DMA) but under supervision. The device which supervises data transfer is named as DMA controller.

1. The sequence of DMA transfer is as follows:

   • Microprocessor initializes the DMAC (DMA controller) by giving the starting address and the number of bytes to be transferred.
   • An I/O device requests the DMAC to perform DMA transfer through the DREQ line.
   • The DMAC in turn sends a request signal to the microprocessor through the HOLD line.
   • The microprocessor finishes the current machine cycle and releases the system bus (gets disconnected from it). It also acknowledges receiving the HOLD signal through the HLDA line.
   • The DMAC acquires control of the system bus. The DMAC sends the DACK signal to the I/O peripheral and the DMA transfer begins.
   • After every byte is transferred, the address register is incremented (or decremented) and the count register is decremented.
   • This continues till the count reaches zero (Terminal count). Now the DMA transfer is completed.
   • At the end of the transfer, the system bus is released by the DMAC by making HOLD = 0. Thus microprocessor takes control of the system bus and continues its operation.

Block diagram of 8237

CAR (Current Address Register):

• The current address register holds a 16-bit memory address used for the DMA transfer.
• Each channel has its own current address register for this purpose.
• When a byte of data is transferred during a DMA operation, CAR is either incremented or decremented depending on how it is programmed.

CWCR (Current word count register):

• The current word count register programs a channel for the number of bytes to transferred during a DMA action.

CR (Command register):

• The command register programs the operation of the 8237 DMA controller.
• transfer mode.
  • Memory-to-memory DMA transfers use DMA channel.
  • DMA channel 0 to hold the source address.
  • DMA channel 1 holds the destination address.

BA (Base Address) and BWC (Base Word Count):

• The Base Address (BA) and Base Word Count (BWC) registers are used when auto-initialization is selected for a channel.
• In auto-initialization mode, these registers are used to reload the CAR and CWCR after the DMA action is completed.

MR (Mode register):

• The mode register programs the mode of operation for a channel.
• Each channel has its own mode register as selected by bit positions 1 and 0.
• Remaining bits of the mode register select operation, auto-initialization, increment/decrement, and mode for the channel.

BR (Bus request register):

• The bus request register is used to request a DMA transfer via software.
• It is very useful in memory-to-memory transfers where an external signal is not available to begin the DMA transfer.

MRSR (Mask register set/reset):

• The mask register set/reset sets or clears the channel mask.
• If the mask is set, the channel is disabled.
• The RESET signal sets all channel masks to disable them.

MSR (Mask register):

• The mask register clears or sets all of the masks with one command instead of individual channels, as with the MRSR.

*SR (Status register):

• The status register shows status of each DMA channel. The TC bits indicate if the channel has reached its terminal count (transferred all its bytes).
• When the terminal count is reached, the DMA transfer is terminated for most modes of operation.
• The request bits indicate whether the DREQ input for a given channel is active.