The 8237 operates in the following modes:

1. Rotating Priority Mode-

• If the RP bit of mode set register is set then the 8237 operates in rotating priority mode.
• After each DMA cycle, the priority of each channel changes.
• Hence all channels will get equal opportunity if they are enabled and their DMA requests exist. Initially, CH-0 gains highest priority while CH-3 gains lowest priority.
• The channel which has just been serviced will get the lowest priority after the DMA cycle and other channels move up to the next higher priority levels.
• The rotating pattern of channels is as shown in the figure below:

1. Fixed Priority Mode-

• If the RP bit of mode set register is reset then 8237 operates in fixed priority mode.
• In fixed priority mode, channel 0 has highest priority and channel 3 has lowest priority.
• The priority is resolved during state 4 of each DMA cycle.

1. Extended Write Mode-

• This mode is used to interface slower devices to the system.
• If the memory device or I/O device connected is slower, then for synchronization READY signal is used.
• In this method, the write signal is delayed by adding wait states into a DMA cycle. This reduces the speed of transfer.
• But in extended write mode, the write signal is extended earlier without adding states i.e. the set up time of write input signal of an I/O device or memory is increased in extended write mode without reducing the speed of transfer.
• This signal allows more time to external logic for deciding if additional wait states are needed.
• If the EW bit of mode set register is set then 8237 generates advanced or extended write control signals ((IOW) ̅ & (MEMW) ̅) i.e. the write control signals will go LOW, one clock cycle earlier as shown in the figure below:

1. TC Stop Mode-

• If the TC stop bit in mode set register is set then 8237 disables the channel whose TC is reached. Thus it stops further DMA operations on that channel.
• If the TC stop bit is reset then the TC have no effect on channel, corresponding channel must be disabled by the microcomputer system through software.
• The TC stop bit option should be common for all channels.

1. Auto-load Mode-

• If AL bit of mode set register is set, the 8237 operates in auto-load mode.
• In this mode, the data is transferred by channel 2 only i.e. other channels are not used for data transfer.
• It can be used for repeat block or block chaining operations.

• Repeat block operation:

  • If the AL bit is set, the parameters (memory address and terminal count) of CH-2 are duplicated into CH-3 register.

  • The new parameters are not written into the CH-3 registers.

  • The CH-2 transfers first DMA block between memory and I/O devices. After transferring first DMA block, the 8237 executes an update cycle. During this cycle the contents of CH-3 register are transferred to CH-2 register and update flag is set in status register.

  • Thus, the repeat block operation continues with the programming of only CH-2.

• Block chaining operation:

  • In this operation CH-2 transfers two or more different data blocks. CH-3 must be loaded with different parameters after initialization of CH-2 registers.
  • In this mode, both the channels have to be enabled.
  • The TC stop bit is irrelevant.
  • Initially, CH-2 and CH-3 register are initialized with block 1 and block 2 parameters respectively. Then, CH-2 transfers data block.
  • During last DMA cycle it activates TC signal and sets the update flag.
  • The 8237 executes an update cycle and transfers contents of CH-3 registers into CH-2 registers.
  • The update flag is cleared at the end of first DMA cycle of next data block.
  • The microprocessor writes new parameters (block parameter) into CH-3 registers.
  • The CH-2 then transfers second byte of next data block. In this way, CH-2 transfers two or more data blocks.
  • The TC signal can be used to interrupt the microprocessor to load block parameters.
  • The auto-load timing diagram is shown in the figure below: