1. In I/O data transfer, data is transferred by using microprocessor. The microprocessor will read data from I/O device and then will write data to memory.
2. In this case, there are two operations for single data transfer. If the data is less then microprocessor will not waste its time transferring data from I/O to memory or back.
3. But suppose data is huge then the transfer rate from I/O to memory or back will slow down because of microprocessor intervention.
4. In such case, to speed up the process of transferring the data, I/O should have direct access to memory.
5. It can have Direct Memory Access (DMA) but under supervision. The device which supervises data transfer is named as DMA controller.

The sequence of DMA transfer is as follows:

• Microprocessor initializes the DMAC (DMA controller) by giving the starting address and the number of bytes to be transferred.
• An I/O device requests the DMAC to perform DMA transfer through the DREQ line.
• The DMAC in turn sends a request signal to the microprocessor through the HOLD line.
• The microprocessor finishes the current machine cycle and releases the system bus (gets disconnected from it). It also acknowledges receiving the HOLD signal through the HLDA line.
• The DMAC acquires control of the system bus. The DMAC sends the DACK signal to the I/O peripheral and the DMA transfer begins.
• After every byte is transferred, the address register is incremented (or decremented) and the count register is decremented.
• This continues till the count reaches zero (Terminal count). Now the DMA transfer is completed.
• At the end of the transfer, the system bus is released by the DMAC by making HOLD = 0. Thus microprocessor takes control of the system bus and continues its operation.

DMA Controller: Data Transfer Modes

The DMA controller functions as a bus master and bus slave. It performs data transfer operations. DMA controlled input/output is further divided into the following categories:

1. Burst or Block Transfer DMA-

   • It is the fastest DMA mode.
   • In this mode, two or more data bytes are transferred continuously.
   • The microprocessor is disconnected from the system bus during DMA transfer i.e. the microprocessor cannot execute its own program during this transfer.
   • N number of DMA cycles are added into the machine cycles of the microprocessor where N is number of bytes to be transferred.
   • In this mode, the DMA controller sends HOLD signal to the microprocessor and waits for HLDA signal.
   • After receiving HLDA signal, the DMA controller gains control of the system bus and execute a DMA cycle to transfer one byte.
   • After transferring one byte, it increments memory address, decrements counter and transfers next byte.
   • In this way, it transfers all data bytes between memory and I/O devices. After transferring all data bytes, the DMA controller disables HOLD signal and enters in to slave mode.

2. Cycle Steal or Single Byte Transfer DMA-

   • In cycle steal transfer only one byte of data is transferred at a time.
   • This type of DMA is slower than burst DMA.
   • In this mode, only one DMA cycle is added between two machine cycles of the microprocessor, hence the instruction execution speed of the microprocessor is reduced slightly.
   • In this mode the DMA controller sends HOLD signal to the microprocessor and waits for HLDA signal.
   • After receiving HLDA signal, the DMA controller gains control of the system bus and execute only one DMA cycle.
   • After transferring one byte, it disables HOLD signal and enters into slave mode.
   • The microprocessor then gains control of the system bus and executes next machine cycle. If the count is not zero and next data is available then the DMA controller sends HOLD signal to the microprocessor and transfers next byte of data block.

3. Transparent or Hidden DMA Transfer-

   • The microprocessor executes some states during which it floats the address and data buses.
   • During these states, the microprocessor is isolated from the system bus.
   • The DMA controller transfers data between memory and I/O devices during these states. This operation is transparent to microprocessor.
   • This is the slowest DMA transfer. In this mode, the instruction execution speed of microprocessor is not reduced. But the transparent DMA requires logic to detect the states when the microprocessor is floating the buses.