Features:

1. It is a LSI chip which manages 8 levels of interrupts i.e. it is used to implement 8 level interrupt systems.
2. It can be cascaded in a master slave configuration to handle up to 64 levels of interrupts.
3. It can identify the interrupting device.
4. It can resolve the priority of interrupt requests i.e. it does not require any external priority resolver.
5. It can be operated in various priority modes such as fixed priority and rotating priority.
6. The interrupt requests are individually mask-able.
7. The operating modes and masks may be dynamically changed by the software at any time during execution of programs.
8. It accepts requests from the peripherals, determines priority of incoming request, checks whether the incoming request has a higher priority value than the level currently being serviced and issues an interrupt signal to the microprocessor.
9. It provides 8 bit vector number as an interrupt information.
10. It does not require clock signal.
11. It can be used in polled as well as interrupt modes.
12. The starting address of vector number is programmable.
13. It can be used in buffered mode.

The block diagram of 8259 is shown in the figure below:

It contains following blocks-

1. Data bus buffer-

• It is used to transfer data between microprocessor and internal bus.

1. Read/write logic-

• It sets the direction of data bus buffer.
• It controls all internal read/write operations.
• It contains initialization and operation command registers.

1. Cascaded buffer and comparator-

• In master mode, it functions as a cascaded buffer. The cascaded buffers outputs slave identification number on cascade lines.
• In slave mode, it functions as a comparator. The comparator reads slave identification number from cascade lines and compares this number with its internal identification number.
• In buffered mode, it generates an (EN) ̅ signal.

1. Control logic-

• It generates an INT signal. In response to an (INTA) ̅ signal, it releases three byte CALL address or one byte vector number.
• It controls read/write control logic, cascade buffer/comparator, in service register, priority resolver and IRR.

1. Interrupt request register-

• It is used to store all pending interrupt requests.
• Each bit of this register is set at the rising edge or at the high level of the corresponding interrupt request line.
• The microprocessor can read contents of this register by issuing appropriate command word.

1. In service register (InSR)-

• It is used to store all interrupt levels currently being serviced.
• Each bit of this register is set by priority resolver and reset by end of interrupt command word.
• The microprocessor can read contents of this register by issuing appropriate command word.

1. Priority resolver-

• It determines the priorities of the bit set in the IRR. To make decision, the priority resolver looks at the ISR.
• If the higher priority bit in the InSR is set then it ignores the new request.
• If the priority resolvers find that the new interrupt has a higher priority than the highest priority interrupt currently being serviced and the new interrupt is not in service, then it will set appropriate bit in the InSR and send the INT signal to the microprocessor for new interrupt request.

1. Interrupt mask register (IMR)-

• It is a programmable register.
• It is used to mask unwanted interrupt request by writing appropriate command word.
• The microprocessor can read contents of this register without issuing any command word.