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Explain interfacing of 8259 with 8086 (Cascade mode)

written 8.3 years ago by teamques10 ★ 68k

modified 2.0 years ago by sagarkolekar ★ 11k

microprocessors and microcontrollers

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written 8.3 years ago by teamques10 ★ 68k

1. When more than one 8259s are connected to the microprocessor, it is called as a cascaded configuration.
2. A cascaded configuration increases the number of interrupts handled by the system.
3. As the maximum number of 8259s interfaced can be 9 (1 master and 8 slaves) the maximum number of interrupts handled can be 64.
4. The master 8259 has $\overline{SP}/ \overline{EN}= +5V$ and the slave has $\overline{SP}/ \overline{EN}= 0V$.
5. Each slave’s INT output is connected to the IR input of the master.
6. The INT output of the master is connected to the INTR input of the microprocessor.
7. The master addresses the individual slaves through CAS2, CAS1 and CAS0 lines connected from the master to each of the slaves.
8. First the INTR signal of the microprocessor should be enabled using the STI instruction.
9. Each 8259 (master or slave) has its own address and has to be initialized separately by giving ICWs as per requirement.
10. When an interrupt request occurs on a slave, the events are performed:
11. The slave 8259 resolves the priority of the interrupt and sends the interrupt to the master 8259.
12. The master resolves the priority among the slaves and sends the interrupt to the microprocessor.
13. The microprocessor finishes the current instruction and responds to the interrupt by sending 2 $\overline{INTA}$ pulses.
14. In response to the first $\overline{INTA}$ pulse, the following events occur-
    • The master sends the 3 bit slave identification number on the CAS lines.
    • The master sets the corresponding bit in its InSR.
    • The slave identifies its number on the CAS lines and sets the corresponding bit in its InSR.
15. In response to the second $\overline{INTA}$ pulse, the slave places vector number N on the data bus.
16. During the 2nd $\overline{INTA}$ pulse, the InSR bit of the slave is cleared in AEOI mode otherwise it is cleared by the EOI command at the end of the ISR.
17. The microprocessor pushes the contents of flag register, CS, IP in to the stack; clears IF and TF and transfers program to the address of the ISR.
18. The ISR thus begins.

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