8087 Math Coprocessor:

1. Intel 8087 is a processor with architecture and instruction set optimized for performing complicated arithmetic operations.
2. An 8087 is along with the host microprocessor 8086 rather than serving as the main processor itself. Therefore, it is referred to as the coprocessor.
3. An 8087 instruction may perform a given mathematical computation 100 times faster than the equivalent sequence of 8086 instructions.
4. 8087 is an actual processor with its own specialized instruction set. Instructions for 8087 are written in the program as needed, interspersed with 8086 instructions.
5. As the 8086 fetches instruction bytes from the memory and puts them in its queue, the 8087 also reads these instruction bytes and puts them in its queue. The 8087 decodes each instruction that comes into its queue.
6. When 8087 decodes an instruction from its queue and finds that it is an 8086 instruction, the 8087 simply treats the instruction as NOP.
7. Likewise, when the 8086 decodes an instruction from its queue and finds that it is an 8087 instruction, the 8086 simply treats the instruction as NOP or in some cases reads a data word from the memory for the 8087.
8. Each processor decodes all instructions in the fetched instruction byte stream but executes only its own instructions.

Interfacing of 8086 with 8087:

1. As a coprocessor (8087) is connected to 8086, 8086 operates in maximum mode. Thus the $MN/ \overline{MX}$ is grounded.
2. 8284 provides the common CLK, RESET and READY signals. 8282 are used to latch the address. 8286 are used as data trans-receivers. 8288 generates control signals using $ \overline{S_2} , \overline{S_1} \ \ and \ \ \overline{S_0}$ as input from the currently active processor. 8259 PIC is used to accept the interrupt from 8087 and send it to the microprocessor.
3. This interface is also called as coprocessor configuration. Here 8086 is called as the host and 8087 as coprocessor as it cannot operate all by itself.
4. We write a homogeneous program which contains both 8086 as well as 8087 instructions.
5. Only 8086 can fetch instructions but these instructions also enter 8087. 8087 treats 8086 instructions as NOP.
6. ESC is used as a prefix for 8087 instructions. When as instruction with ESC prefix (5 MSB bits as 11011) is encountered, 8087 is activated.
7. The ESC instruction is decoded by both 8086 and 8087.
8. If the 8087 instruction has only an opcode (no operands) then 8087 will start execution and 8086 will immediately move its next instruction.
9. But if the instruction requires a memory operand, then 8086 will have to fetch the first word of the operand as 8087 cannot calculate the physical address. This word will be captured by 8087. Now the remaining words (for a large operand) can be fetched by 8087 by simply incrementing the address of the first word. Thus 8087 need help from 8086.
10. Once 8087 gets its operand, it begins processing by making the BUSY output high. This BUSY output is connected to the TEST input of the microprocessor. Now 8087 execute its instruction and 8086 moves ahead with its next instruction. Hence multiprocessing takes place.
11. During execution, if 8087 needs to read/ write more words from the memory, then it does so by stealing bus cycles from the microprocessor in the following manner. The $\overline{RQ}/ \overline{GT_0}$ of 8087 is connected to $\overline{RQ}/ \overline{GT_0}$ of the microprocessor. 8087 gives an active low request pulse. 8086 completes the current bus cycle and gives the grant pulse and enters the hold state. 8087 uses the shared system bus to perform the data transfer with the memory. 8087 gives the release pulse and returns the system bus back to the microprocessor.
12. If 8086 requires the result of the 8087 operation, it first executes the WAIT instruction. WAIT makes the microprocessor check the TEST pin. If the TEST pin is high (8087 is BUSY), then the microprocessor enters WAIT state. It comes out of it only when TEST is low (8087 has finished its execution). Thus 8086 get the correct result of an 8087 operation.
13. During the execution if an exception occurs, which is unmasked, 8087 interrupts microprocessor using the INT output pin through the PIC 8259.
14. The $QS_0$ and $QS_1$ lines are used by 8087 to monitor the queue of 8086. 8087 needs to know when 8086 will decode the ESC instruction so it synchronizes its queue with 8086 using $QS_0$ and $QS_1$ as follows:

This is the complete inter-processor communication between 8086 and 8087 to form a homogeneous system.