As 8086 does 2-stage pipelining (overlapping fetching and execution), its architecture is divided into two units:

1. Bus Interfacing Unit (BIU)
2. Execution Unit (EU)

Bus Interfacing Unit (BIU)-

• It provides the interface of 8086 to external memory and I/O devices.
• It operates with respect to bus cycles (machine cycles). This means it performs various machine cycles such as memory read, I/O read etc. to transfer data with memory and I/O devices.
• BIU performs the following functions-
  • It generates the 20 bit physical address for memory access.
  • It fetches instruction from memory.
  • It transfers data to and from the memory and I/O.
  • It supports pipelining using the 6 byte instruction queue.

The main components of the BIU are as follows:

• Segment registers-

  • CS register: CS holds the base address for the Code Segment. All programs are stored in the Code Segment. CS is multiplied by 10H to give the 20 bit physical address of the Code Segment. E.g. If CS = 4321H then CS x 10H = 43210H→ Starting address of Code Segment.
  • DS register: DS holds the base address for the Data Segment. It is multiplied by 10H to give the 20 bit physical address of the Data Segment. E.g. If DS = 4321H then DS x 10H = 43210H→ Starting address of Data Segment.
  • SS register: SS holds the base address for the Stack Segment. It is multiplied by 10H to give the 20 bit physical address of the Stack Segment. E.g. If SS = 4321H then SS x 10H = 43210H→ Starting address of Stack Segment.
  • ES register: ES holds the base address for the Extra Segment. It is multiplied by 10H to give the 20 bit physical address of the Extra Segment. E.g. If ES = 4321H then ES x 10H = 43210H→ Starting address of Code Segment.

• Instruction Pointer (IP)-

  • It is a 16 bit register. It holds offset of the next instructions in the Code Segment.
  • Address of the next instruction is calculated as CS x 10H + IP.
  • IP is incremented after every instruction byte is fetched.
  • IP gets a new value whenever a branch occurs.

• Address Generation Circuit-

  • The BIU has a Physical Address Generation Circuit. It generates the 20 bit physical address using Segment and Offset addresses using the formula: Physical Address = Segment Address x 10H + Offset Address

• 6 Byte Pre-fetch Queue-

  • It is a 6 byte first in first out (FIFO) RAM used to implement pipelining. Fetching the next instruction while executing the current instruction is called pipelining.
  • BIU fetches the next six instruction bytes from the Code Segment and stores it into the queue.
  • Execution Unit (EU) removes instructions from the queue and executes them. The queue is refilled when at least two bytes are empty as 8086 has a 16 bit data bus. Pipelining increases the efficiency of the microprocessor.
  • Pipelining fails when a branch occurs as the pre-fetched instructions are no longer useful.
  • Hence as soon as 8086 detects a branch operation, it clears/discards the entire queue.
  • Now, the next six bytes from the new location (branch address) are fetched and stored in the queue and pipelining continues.

Execution Unit (EU)-

• It fetches instructions from the Queue in BIU, decodes and executes them.
• It performs arithmetic, logic and internal data transfer operations within the microprocessor.
• It sends request signals to the BIU to access the external module.
• It operates with respect to T-stats (clock cycles) and does not depend upon which machine cycle is being performed by the BIU.

The main components of the EU are as follows:

• General purpose registers- 8086 microprocessor has four 16 bit general purpose registers AX, BX, CX and DX. These are available to the programmer for storing values during programs. Each of these can be divided into two 8 bit registers such as AH, Al; BH, BL; etc. Beside their general use, these registers also have some specific functions.

  • AX register (16 bits): It holds operands and results during multiplication and division operations. All I/O data transfers using IN and OUT instructions use A register (AL/AH or AX). It functions as accumulator during string operations.
  • BX register (16 bits): It holds the memory address (offset address) in indirect addressing modes.
  • CX register (16 bits): It holds count for instructions like loop, rotate, shift and string operations.
  • DX register (16 bits): It is used with AX to hold 32 bit values during multiplication and division. It is used to hold the address of the I/O port in indirect I/O addressing mode.

• Special purpose registers-

  • Stack Pointer (SP 16 bits): It holds offset address of the top of the Stack. Stack is a set of memory locations operating in LIFO manner. Stack is present in the memory in Stack Segment. It is used during instructions like PUSH, POP, CALL, RET etc.
  • Base Pointer (BP 16 bits): BP can hold offset address of any location in the stack segment. It is used to access random locations of the stack.
  • Source Index (SI 16 bits): It is normally used to hold the offset address for Data Segment but can also be used for other segments using Segment Overriding. It holds offset address of source data in Data Segment during string operations.
  • Destination Index (DI 16 bits): It is normally used to hold the offset address for Extra Segment but can also be used for other segments using Segment Overriding. It holds offset address of destination in Extra Segment during string operations.

• ALU (Arithmetic Logic Unit) - It has a 16 bit ALU. It performs 8 and 16 bit arithmetic and logic operations.

• Operand register- It is a 16 bit register used by the control register to hold the operands temporarily. It is not available to the programmer.
• Instruction Register and Instruction Decoder- The EU fetches an opcode from the queue into the instruction register. The instruction decoder decodes it and sends the information to the control circuit for execution.
• Flag register (16 bits)-
  • It has 9 flags.
  • These flags are of two types: 6 Status flags namely carry flag, parity flag, auxiliary carry flag, zero flag, sign flag and 3 Control flags namely trap flag, interrupt flag and direction flag.
  • Status flags are affected by the ALU after every arithmetic or logic operation. They give the status of the current result.
  • The Control flags are used to control certain operations. They are changed by the programmer.

Need for memory segmentation:

1. The BIU (Bus Interfacing Unit) contains four special purpose registers called as segment registers. These are Code Segment (CS) register, Stack Segment (SS) register, Extra Segment (ES) register and Data Segment (DS) register. All these are 16 bit registers.
2. The number of address lines in 8086 is 20. So the 8086 BIU will send out a 20 bit address in order to access one of the 1,048,576 or 1MB memory locations.
3. But it is interesting to note that the 8086 does not work the whole 1MB memory at any given time. However it works with only four 64 KB segments within the whole 1 MB memory.
4. The four segment registers actually contain the upper 16 bits of the starting addresses of the four memory segments of 64 KB each with which the 8086 is working at that instant of time.
5. Each segment is made up of memory contiguous memory locations. It is independent, separately addressable unit.
6. Segment registers are very useful for large programming tasks that require isolation of program code from the data code or isolation of module data from the stack information etc.
7. Segmentation builds relocatable and re-entrant programs easily. In many cases the task of relocating a program simply requires moving the program code and then adjusting the code segment register to point to the base of the new code area.
8. It allows to extend the address ability of a processor i.e. segmentation allows the use of 16 bit registers to give an addressing capability of 1 MB. Without segmentation, it would require 20 bit registers.