The architecture is divided into two units:

1. Bus Interface Unit (BIU) 2. Execution Unit (EU)

BUS INTERFACE UNIT (BIU)

• It provides the interface of 8086 to other devices.
• It operates w.r.t. Bus cycles. This means it performs various machine cycles such as Memory Read, IO Write etc to transfer data with Memory and I/O devices.
• It also generates the 20-bit physical address for memory access, fetches instruction from memory, transfers data to and from the memory and IO.
• It supports Pipelining using the 6-byte instruction queue.

The main components of the BIU are as follows:
SEGMENT REGISTERS:

• CS Register: CS holds the base (Segment) address for the Code Segment. All programs are stored in the Code Segment. It is multiplied by 10H (16d), to give the 20-bit physical address of the Code Segment. CS register cannot be modified by executing any instruction except branch instructions.

• DS Register: DS holds the base (Segment) address for the Data Segment. It is multiplied by 10H (16d), to give the 20-bit physical address of the Data Segment. Eg: If DS = 4321H then DS × 10H = 43210H è Starting address of Data Segment.

• SS Register: SS holds the base (Segment) address for the Stack Segment. It is multiplied by 10H (16d), to give the 20-bit physical address of the Stack Segment.

• ES Register: ES holds the base (Segment) address for the Extra Segment. It is multiplied by 10H (16d), to give the 20-bit physical address of the Extra Segment.

Instruction Pointer (IP register): It is a 16-bit register. It holds offset of the next instruction in the Code Segment. Address of the next instruction is calculated as CS x 10H + IP. IP is incremented after every instruction byte is fetched. IP gets a new value whenever a branch occurs.

Address Generation Circuit: The BIU has a Physical Address Generation Circuit. It generates the 20-bit physical address using Segment and Offset addresses using the formula: Physical Address (20 bit) = Segment Address (16 bit) X 10H + Offset Address (16 bit)

Pipelining: It is a 6-byte FIFO RAM used to implement Pipelining. Fetching the next instruction while executing the current instruction is called Pipelining. BIU fetches the next “six instruction-bytes” from the Code Segment and stores it into the queue. Execution Unit (EU) removes instructions from the queue and executes them.

Execution Unit (EU)

• It fetches instructions from the Queue in BIU, decodes and executes them.

• It performs arithmetic, logic and internal data transfer operations. It sends request signals to the BIU to access the external module. It operates in synchronization with T-States (clock cycles).

The main components of the EU are as follows:

a) General Purpose Registers: 8086 has four 16-bit general-purpose registers AX, BX, CX and DX. These are available to the programmer, for storing values during programs. Each of these can be divided into two 8-bit registers such as AH, AL; BH, BL; CL, CH and DL, DH. Beside their general use, these registers also have some specific functions.

• AX Register (16-Bits): It holds operands and results during multiplication and division operations. All IO data transfers using IN and OUT instructions use A register (AL/AH or AX). It functions as accumulator during string operations.
• BX Register (16-Bits): It holds the memory address (offset address), in Indirect Addressing modes.
• CX Register (16-Bits): It holds count for instructions like: Loop, Rotate, Shift and String Operations.
• DX Register (16-Bits): It is used with AX to hold 32 bit values during Multiplication and Division. It is used to hold the address of the IO Port in indirect IO addressing mode.

b) Special Purpose Registers

• Stack Pointer (SP 16-Bits): It is holds offset address of the top of the Stack. Stack is a set of memory locations operating in LIFO manner. SP is used with the SS Register to calculate physical address for the Stack Segment. It used during instructions like PUSH, POP, CALL, RET etc. During PUSH instruction, SP is decremented by 2 and during POP it is incremented by 2.

• Base Pointer (BP 16-Bits): It holds the offset address of any location in the stack segment. It is used to access random locations of the stack.

• Source Index (SI 16-Bits): It is normally used to hold the offset address for Data segment but can also be used for other segments using Segment Overriding. It holds offset address of source data in Data Segment, during String Operations.

• Destination Index (DI 16-Bits): It is normally used to hold the offset address for Extra segment but can also be used for other segments using Segment Overriding. It holds offset address of destination in Extra Segment, during String Operations.

c) ALU (16-Bits): It has a 16-bit ALU. It performs 8 and 16-bit arithmetic and logic operations.

d) Instruction Register and Instruction Decoder (Present inside the Control Unit): The EU fetches an opcode from the queue into the Instruction Register. The Instruction Decoder decodes it and sends the information to the control circuit for execution.