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Draw a circuit diagram for 3-bit asynchronous binary down counter using master-slave JK flip-flops.
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Q. Draw a circuit diagram for 3-bit asynchronous binary down counter using master-slave JK flip-flops. Show the output of each flip-flop with reference to the clock & justify that the down counting action. Also prove from the timing diagram that the counters is "divide by 8" counter.
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