Design a 8086 based system with following specifications

• CPU at 10MHz in minimum mode operation

• 32 KB SRAM using 8 KB devices

• 64 KB EPROM using 16 KB devices

• One 8255 PPI for keyboard interface Design system with absolute decoding. Clearly show memory address map and I/O address map. Draw a neat schematic for chip selection logic.

Step 1: Total EPROM required = 64 KB

Chip size available = 16 KB

$∴ \text{Number of chips required} = \frac{64 KB}{16 KB} = 4$

$∴ \text{Number of sets required} = \frac{Number of chips}{Number of banks} = \frac{4}{2} = 2$

SET 1: Ending address of SET 1 = FFFFFH

SET size = Chip size x 2 = 16 KB x 2 = 32 KB

i.e. $\frac{0000}{0} \frac{0111}{7} \frac{1111}{F} \frac{1111}{F} \frac{1111}{F}$

$\text{Starting address = Ending address – SET size} \\ \hspace{2.8cm} = FFFFFH – 07FFFH \\ \hspace{2.8cm} = F8000H$

SET 2: Ending address of SET 2 = F7FFFH (previous ending - 1)

SET size = Chip size x 2 = 16 KB x 2 = 32 KB

i.e. $\frac{0000}{0} \frac{0111}{7} \frac{1111}{F} \frac{1111}{F} \frac{1111}{F}$

$\text{Starting address = Ending address – SET size} \\ \hspace{2.8cm} = F7FFFH – 07FFFH \\ \hspace{2.8cm} = F0000H$

Step 2: Total RAM required = 32 KB

Chip size available = 8 KB

$∴ \text{Number of chips required} = \frac{32 KB}{8 KB} = 4$

$∴ \text{Number of sets required} = \frac{Number of chips}{Number of banks} = \frac{4}{2} = 2$

SET 1: Starting address = 00000H

SET size = Chip size x 2 = 8 KB x 2 = 32 KB

i.e. $\frac{0000}{0} \frac{0011}{3} \frac{1111}{F} \frac{1111}{F} \frac{1111}{F}$

$\text{Ending address = Starting address – SET size} \\ \hspace{2.8cm} = 04000H + 03FFFH \\ \hspace{2.8cm} = 07FFFH$

SET 2: Starting address = 04000H (previous ending - 1)

SET size = Chip size x 2 = 8 KB x 2 = 32 KB

i.e. $\frac{0000}{0} \frac{0011}{3} \frac{1111}{F} \frac{1111}{F} \frac{1111}{F}$

$\text{Ending address = Starting address – SET size} \\ \hspace{2.8cm} = 04000H – 03FFFH \\ \hspace{2.8cm} = 07FFFH$

Step 4: Final Implementation: